Satya V. Nitta  Satya V. Nitta photo       

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Master Inventor. Program Leader. Cognitive Computing for Education.
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash1557

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2014

Methods for fabrication of an air gap-containing interconnect structure
Lawrence A Clevenger, Maxime Darnon, Satyanarayana V Nitta, Anthony D Lisi, Qinghuang Lin
US Patent 8,642,252

Reliable physical unclonable function for device authentication
John Bruley, Vijay Narayanan, Dirk Pfeiffer, Jean-Oliver Plouchart, Peilin Song
US Patent 8,741,713

Beol structures incorporating active devices and mechanical strength
Stephen M Gates, Daniel C Edelstein, Satyanarayana V Nitta
US Patent App. 14/148,573

Air gap-containing interconnect structure having photo-patternable low k material
Lawrence A Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D Lisi, Satyanarayana V Nitta
US Patent 8,629,561


2013

Method for fabricating air gap interconnect structures
Kaushik Chanda, Cathryn J Christiansen, Daniel C Edelstein, Satyanarayana V Nitta, Son V Nguyen, Shom Ponoth, Hosadurga Shobha
US Patent 8,383,507

Crenulated wiring structure and method for integrated circuit interconnects
Griselda Bonilla, Elbert E Huang, Satyanarayana V Nitta, Shom Ponoth
US Patent 8,421,239

Semiconductor chips including passivation layer trench structure
Deepak Kulkarni, Michael W Lane, Satyanarayana V Nitta, Shom Ponoth
US Patent 8,440,505


Multi component dielectric layer
Stephen M Gates, Alfred Grill, Son Van Nguyen, Satyanarayana Venkata Nitta
US Patent 8,357,608

Selectively coated self-aligned mask
Matthew E Colburn, Stephen M Gates, Jeffrey C Hedrick, Elbert Huang, Satyanarayana V Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian
US Patent 8,491,987


2012

Method for air gap interconnect integration using photo-patternable low k material
Lawrence A Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D Lisi, Satyanarayana V Nitta
US Patent 8,241,992

Interlevel Dielectric Stack for Interconnect Structures
Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J Haigh, Satyanarayana V Nitta, others
US Patent App. 13/344,009

Reversing tone of patterns on integrated circuit and nanoscale fabrication
Lawrence A Clevenger, Maxime Darnon, Anthony D Lisi, Satya V Nitta
US Patent 8,183,694

Interconnect structures with ternary patterned features generated from two lithographic processes
Matthew E Colburn, Elbert Huang, Satyanarayana V Nitta, Sampath Purushothaman
US Patent 8,338,952

Deep trench crackstops under contacts
Matthew S Angyal, Lawrence A Clevenger, Vincent J McGahay, Satyanarayana V Nitta, Shaoning Yao
US Patent 8,237,246

Microelectronic structure including air gap
Daniel C Edelstein, David V Horak, Elbert E Huang, Satyanarayana V Nitta, Takeshi Nogami, Shom Ponoth, Terry A Spooner
US Patent 8,288,268

Financial Risk Analytics for Service Contracts
Geraldine L Abbott, Sherif A Goma, Allen D Grussing, Richard D Howard, Sinem Guven Kaya, Peter Lorenzen, Sergey Makogon, Satya Nitta, Anatoli Olkhovets, Natalia M Ruderman, others
US Patent App. 13/685,362

Air gap interconnect structures and methods for forming the same
Kaushik Chanda, Cathryn J Christiansen, Daniel C Edelstein, Son V Nguyen, Satyanarayana V Nitta, Shom Ponoth, Hosadurga Shobha
US Patent 8,120,179

Reducing effective dielectric constant in semiconductor devices
Matthew E Colburn, Edward C Cooney III, Timothy J Dalton, Daniel C Edelstein, John A Fitzsimmons, Jeffrey P Gambino, Elbert E Huang, Michael W Lane, Vincent J McGahay, Lee M Nicholson, others
US Patent 8,129,286


2011

Electronics structures using a sacrificial multi-layer hardmask scheme
Matthew Earl Colburn, Ricardo Alves Donaton, Xiao Hu Liu, Conal E Murray, Satyanarayana Venkata Nitta, Sampath Purushothaman, Sujatha Sankaran, Thedorus Eduardos Standaert
US Patent 7,947,907

Method to create region specific exposure in a layer
Christos D Dimitrakopoulos, Daniel C Edelstein, Vincent J McGahay, Satyanarayana V Nitta, Kevin S Petrarca, Shom Ponoth, Shahab Siddiqui
US Patent 7,977,032

Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
Robert L Bruce, Qinghuang Lin, Alshakim Nelson, Satyanarayana V Nitta, Dirk Pfeiffer, Jitendra S Rathore
US Patent App. 13/088,054

Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby
Azeez J Bhavnagarwala, Stephen V Kosonocky, Satyanarayana V Nitta, Sampath Purushothaman
US Patent 7,968,450



Air gap structure having protective metal silicide pads on a metal feature
Griselda Bonilla, Daniel C Edelstein, Satyanarayana V Nitta, Takeshi Nogami, Shom Ponoth, David L Rath, Chih-Chao Yang
US Patent 8,003,520

Method to generate airgaps with a template first scheme and a self aligned blockout mask and structure
Matthew E Colburn, Daniel C Edelstein, Satyanarayana Venkata Nitta, Shom Ponoth, Sampath Purushothaman
US Patent App. 12/983,885

Sub-lithographic dimensioned air gap formation and related structure
Daniel C Edelstein, Nicholas CM Fuller, David V Horak, Elbert E Huang, Wai-kin Li, Anthony D Lisi, Satyanarayana V Nitta, Shom Ponoth
US Patent 7,943,480

Method to generate airgaps with a template first scheme and a self aligned blockout mask
Matthew Earl Colburn, Daniel C Edelstein, Satya Venkata Nitta, Shom Ponth, Sampath Purushothaman
US Patent 7,863,150


2010

Surface treatment for selective metal cap applications
Satya V Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian, Chih-Chao Yang
US Patent 7,830,010

Forming interconnects with air gaps
Samuel SS Choi, Lawrence A Clevenger, Maxime Darnon, Daniel C Edelstein, Satyanarayana Venkata Nitta, Shom Ponoth, Pak Leung
US Patent 7,790,601

Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer
Griselda Bonilla, Lawrence A Clevenger, Elbert E Huang, Satyanarayana V Nitta, Shom Ponoth
US Patent App. 12/887,010

Structures and methods for air gap integration
Lawrence A Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D Lisi, Satyanarayana V Nitta
US Patent App. 12/768,267

Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices
Griselda Bonilla, Christos D Dimitrakopoulos, Alfred Grill, Son V Nguyen, Satyanarayana V Nitta, Darryl D Restaino, Terry A Spooner
US Patent 7,749,892


2009

Method for reversing tone of patterns on integrated circuit and patterning sub-lithography trenches
Lawrence A Clevenger, Maxime Darnon, Anthony D Lisi, Satya V Nitta
US Patent App. 12/510,001

Method to preserve the critical dimension (cd) of an interconnect structure
Griselda Bonilla, Satyanarayana V Nitta, Terry A Spooner
US Patent App. 12/436,459

Methods to mitigate plasma damage in organosilicate dielectrics
John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
US Patent 8,470,706


Multilayer interconnect structure containing air gaps and method for making
Christopher V Jahnes, Satyanarayana V Nitta, Kevin S Petrarca, Katherine L Saenger
US Patent 7,534,696


2008

METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES
Andrew J Kellock, Hyungjun Kim, Satyanarayana V Nitta, Dae-Gyu Park, Sampath Purushothaman, Stephen Rossnagel, Oscar van der Straten
US Patent App. 12/203,338



Interconnect structure with high leakage resistance
Satya V Nitta, Chih-Chao Yang
US Patent App. 12/027,677

Process for preparing electronics structures using a sacrificial multilayer hardmask scheme
Matthew Earl Colburn, Ricardo Alves Donaton, Xiao Hu Liu, Conal E Murray, Satyanarayana Venkata Nitta, Sampath Purushothaman, Sujatha Sankaran, Theodorus Eduardus Fransiscus Maria Standaert
US Patent 7,371,684

Method of forming closed air gap interconnects and structures formed thereby
Matthew E Colburn, Timothy J Dalton, Elbert Huang, Simon M Karecki, Satya V Nitta, Sampath Purushothaman, Katherine L Saenger, Maheswaran Surendra
US Patent 7,393,776

Device and methodology for reducing effective dielectric constant in semiconductor devices
Daniel C Edelstein, Matthew E Colburn, Edward C Cooney III, Timothy J Dalton, John A Fitzsimmons, Jeffrey P Gambino, Elbert E Huang, Michael W Lane, Vincent J McGahay, Lee M Nicholson, others
US Patent 7,405,147

Closed air gap interconnect structure
Matthew E Colburn, Timothy J Dalton, Elbert Huang, Simon M Karecki, Satya V Nitta, Sampath Purushothaman, Katherine L Saenger, Maheswaran Surendra
US Patent 7,361,991


2007

Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby
Griselda Bonilla, Stephen M Gates, Satyanarayana V Nitta, Shom Ponoth, Sampath Purushothaman
US Patent App. 11/672,608



Interconnect structures with engineered dielectrics with nanocolumnar porosity
Charles Black, Matthew E Colburn, Kathryn Guarini, Satya V Nitta, Sampath Purushothaman
US Patent 7,268,432


Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics
Nirupama Chakrapani, Matthew E Colburn, Christos D Dimitrakopoulos, Satyanarayana V Nitta, Dirk Pfeiffer, Sampath Purushothaman
US Patent 7,179,758


2006

Line level air gaps
Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, others
US Patent 7,084,479

Air-gap interconnect structures with selective cap
Daniel C Edelstein, Satyanarayana V Nitta, Shom Ponoth
US Patent App. 11/460,019

Very low effective dielectric constant interconnect Structures and methods for fabricating the same
Donald F Canaperi, Timothy J Dalton, Stephen M Gates, Mahadevaiyer Krishnan, Satya V Nitta, Sampath Purushothaman, Sean PE Smith
US Patent 7,023,093



2005

Method for protecting a semiconductor device from carbon depletion based damage
Griselda Bonilla, Richard Conti, Timothy Dalton, Nicholas Fuller, Kelly Malone, Satyanarayana Nitta, Shom Ponoth
US Patent App. 11/162,219

Semiconductor devices containing a discontinuous cap layer and methods for forming same
Stanley Joseph Whitehair, Stephen McConnell Gates, Sampath Purushothaman, Satyanarayana V Nitta, Maurice McGlashan-Powell, Kevin S Petrarca
US Patent 6,943,451

Fabrication of Interconnect Structures
Elbert Emin Huang, Hyungjun Kim, Robert Dennis Miller, Satyanarayana Venkata Nitta, Sampath Purushothaman
US Patent App. 11/570,014

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
Matthew E Colburn, Stephen M Gates, Jeffrey C Hedrick, Elbert Huang, Satyanarayana V Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian
US Patent 6,911,400


2004

Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby
Azeez Bhavnagarwala, Stephen Kosonocky, Satyanarayana Nitta, Sampath Purushothaman
US Patent App. 10/988,484

Fine-pitch device lithography using a sacrificial hardmask
Timothy J Dalton, Minakshisundaran B Anand, Michael D Armacost, Shyng-Tsong Chen, Stephen M Gates, Stephen E Greco, Simon M Karecki, Satyanarayana V Nitta
US Patent 6,734,096

Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer
Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
US Patent 6,831,366


2003

Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask
Ann Rhea-Helene Fornof, Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V Nitta, Sampath Purushothaman, Christy Sensenich Tyberg
US Patent 6,537,908

Improved formation of porous interconnection layers
Shyng-Tsong Chen, Stephen Gates, Jeffrey Hedrick, Kelly Malone, Satyanarayana Nitta, Christy Tyberg

Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same
Matthew E Colburn, Stephen M Gates, Jeffrey C Hedrick, Elbert Huang, Satyanarayana V Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian
US Patent 6,641,899

Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
US Patent 6,603,204


2002

Multilevel interconnect structure containing air gaps and method for making
Alfred Grill, Jeffrey Hedrick, Christopher Jahnes, Satyanarayana Nitta, Kevin Petrarca, Sampath Purushothaman, Katherine Saenger, others

Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence
Matthew Colburn, Elbert Huang, Satyanarayana Nitta, Sampath Purushothaman, Katherine Saenger

Method for selective extraction of sacrificial place-holding material used in fabrication of air gap-containing interconnect structures
John Michael Cotte, Christopher Vincent Jahnes, Kenneth John McCullough, Wayne Martin Moreau, Satyanarayana Venkata Nitta, Katherine Lynn Saenger, John Patrick Simons
US Patent 6,346,484

Method for forming a porous dielectric material layer in a semiconductor device and device formed
Timothy Joseph Dalton, Stephen Edward Greco, Jeffrey Curtis Hedrick, Satyanarayana V Nitta, Sampath Purushothaman, Kenneth Parker Rodbell, Robert Rosenberg
US Patent 6,451,712

Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material
Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Satyanarayana Venkata Nitta, Kevin S Petrarca, Sampath Purushothaman, Katherine Lynn Saenger, Stanley Joseph Whitehair
US Patent 6,413,852


2001

Interconnect structure with precise conductor resistance and method to form same
Stephen Gates, Jeffrey Hedrick, Satyanarayana Nitta, Sampath Purushothaman, Cristy Tyberg

Spin-on cap layer, and semiconductor device containing same
Timothy Dalton, Stephen Gates, Jeffrey Hedrick, Satyanarayana Nitta, Sampath Purushothaman, Christy Tyberg


Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
Stephen Gates, Jeffrey Hedrick, Satyanarayana Nitta, Sampath Purushothaman, Christy Tyberg