Terence B. (Terry) Hook  Terence B. (Terry) Hook photo       

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logic device design
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2016

Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs
Yuan, Zhi Cheng and Rizwan, Shahriar and Wong, Michael and Holland, Kyle and Anderson, Sam and Hook, Terence B and Kienle, Diego and Gadelrab, Serag and Gudem, Prasad S and Vaidyanathan, Mani
IEEE Transactions on Electron Devices 63(10), 4046--4052, IEEE, 2016
Abstract

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology
Bansal, Anil Kumar and Jain, Ishita and Hook, Terence B and Dixit, Abhisek
IEEE Journal of the Electron Devices Society 4(5), 266--272, IEEE, 2016
Abstract

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon? germanium channel p-type FET for scaled supply voltages
Tiwari, Vishal A and Divakaruni, Rama and Hook, Terence B and Nair, Deleep R
Japanese Journal of Applied Physics 55(4S), 04ED03, IOP Publishing, 2016
Abstract

Vertical Slit FET at 7-nm Node and Beyond
Yang, Ping-Lin and Hook, Terence B and Oldiges, Philip J and Doris, Bruce B
IEEE Transactions on Electron Devices 63(8), 3327--3334, IEEE, 2016
Abstract


2015

Transistor Matching and Fin Angle Variation in FinFET Technology
Agarwal, Samarth and Hook, Terence B and Bajaj, Mohit and McStay, Kevin and Wang, Weike and Zhang, Yanting
IEEE Transactions on Electron Devices 62(4), 1357--1359, IEEE, 2015
Abstract

Super fast physics-based methodology for accurate memory yield prediction
Joshi, Rajiv V and Kim, Keunwoo and Kanj, Rouwaida and Bhoj, Ajay N and Ziegler, Matthew M and Oldiges, Phil and Kerber, Pranita and Wong, Robert and Hook, Terence and Saroop, Sudesh and others
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(3), 534--543, IEEE, 2015
Abstract

Nanowire FET design for 7-nm SOI-CMOS technology
Jain, Ishita and Bansal, Anil K and Dixit, Abhisek and Hook, Terence B
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, pp. 1--3
Abstract

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
Kim, Seong-Dong and Guillorn, Michael and Lauer, Isaac and Oldiges, Phil and Hook, Terence and Na, Myung-Hee
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, pp. 1--3
Abstract


2014

Impact of fin sidewall taper angle on sub-14 nm FinFET device performance
Dixit, Abhisek and Hook, Terence B and Johnson, Jeffrey B and Nowak, EJ and Murali, Kota V
Physics of Semiconductor Devices, pp. 5--8, Springer, 2014
Abstract

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
Lu, Darsen and Morin, Pierre and Sahu, Bhagawan and Hook, Terence B and Hashemi, Pouya and Scholze, Andreas and Kim, Bomsoo and Kerber, Pranita and Khakifirooz, Ali and Oldiges, Philip and others
ECS Transactions 64(6), 337--345, The Electrochemical Society, 2014
Abstract

SOI FinFET versus bulk FinFET for 10nm and below
Hook, Terence B and Allibert, F and Balakrishnan, K and Doris, Bruce and Guo, Dechao and Mavilla, Narasimha and Nowak, E and Tsutsui, G and Southwick, R and Strane, J and others
2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1--3
Abstract


2013

Efficient and accurate schematic transistor model of FinFET parasitic elements
Lu, Ning and Hook, Terence B and Johnson, Jeffrey B and Wermer, Carl and Putnam, Christopher and Wachnik, Richard A
IEEE electron device letters 34(9), 1100--1102, Institute of Electrical and Electronics Engineers, 2013
Abstract

FINFET isolation approaches and ramifications: Bulk vs. SOI
Hook, Terence
FDSOI Workshop at Hsinchu, 2013
Abstract


2012

Fully depleted devices for designers: FDSOI and FinFETs
Hook, Terence B
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, pp. 1--7
Abstract


2011

Ultra-thin body and BOX (UTBB) device for aggressive scaling of CMOS technology
Liu, Qing and Yagishita, Atsushi and Kumar, Arvind and Loubet, Nicolas and Yamamoto, Toyoji and Kulkarni, Pranita and Monsieur, Frederic and Khakifirooz, Ali and Ponoth, Shom and Cheng, Kangguo and others
ECS Transactions 34(1), 37--42, The Electrochemical Society, 2011
Abstract

Anomalous dependence of threshold voltage mismatch of short-channel transistors
Hook, Terence B and Johnson, Jeffrey B and Shah, Jay
IEEE Transactions on Electron Devices 58(8), 2805--2807, IEEE, 2011
Abstract

TCAD study of back-gate biasing in UTBB
Hook, Terence B and Furkay, Stephen and Kulkarni, Pranita and Monsieur, Frederic
SOI Conference (SOI), 2011 IEEE International, pp. 1--2
Abstract

Comment on “Channel Length and Threshold Voltage Dependence of a Transistor Mismatch in a 32-nm HKMG Technology”
Hook, Terence B and Johnson, Jeffrey B and Cathignol, Augustin and Cros, Antoine and Ghibaudo, G{'e}rard
IEEE Transactions on Electron Devices 4(58), 1255--1256, 2011
Abstract

Transistor matching and silicon thickness variation in ETSOI technology
Hook, Terence B and Vinet, Maud and Murphy, Richard and Ponoth, Shom and Grenouillet, Laurent
Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 5--7
Abstract

Transistor mismatch properties in deep-submicrometer CMOS technologies
Yuan, Xiaobin and Shimizu, Takashi and Mahalingam, Umashankar and Brown, Jeffrey S and Habib, Kazi Z and Tekleab, Daniel G and Su, Tai-Chi and Satadru, Sarkar and Olsen, C Michael and Lee, Hyunwoo and others
IEEE Transactions on Electron Devices 58(2), 335--342, IEEE, 2011
Abstract


2010

Channel length and threshold voltage dependence of transistor mismatch in a 32-nm HKMG technology
Hook, Terence B and Johnson, Jeffrey B and Han, Jin-Ping and Pond, Andrew and Shimizu, Takashi and Tsutsui, Gen
IEEE Transactions on Electron Devices 57(10), 2440--2447, IEEE, 2010
Abstract


2008

SOI antennas and wafer bulk connection
Hook, Terence B and Pelella, Mario M
2008 IEEE International SOI Conference
Abstract

SOI chip design and charging damage
Hook, Terence B
2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp. 83--86
Abstract

Gate-induced-drain-leakage current in 45-nm CMOS technology
Yuan, Xiaobin and Park, Jae-Eun and Wang, Jing and Zhao, Enhai and Ahlgren, David C and Hook, Terence and Yuan, Jun and Chan, Victor WC and Shang, Huiling and Liang, Chu-Hsin and others
IEEE Transactions on Device and Materials Reliability 8(3), 501--508, IEEE, 2008
Abstract

Analysis and modeling of threshold voltage mismatch for CMOS at 65 nm and beyond
Johnson, Jeffrey B and Hook, Terence B and Lee, Yoo-Mi
IEEE electron device letters 29(7), 802--804, Institute of Electrical and Electronics Engineers, 2008
Abstract


2007

Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
Yuan, Xiaobin and Park, Jae-Eun and Wang, Jing and Zhao, Enhai and Ahlgren, David and Hook, Terence and Yuan, Jun and Chan, Victor and Shang, Huiling and Liang, Chu-Hsin and others
2007 IEEE International Integrated Reliability Workshop Final Report, pp. 70--73
Abstract


2006

Charging Damage and Product Impact in a Bulk CMOS Technology
Hook, Terence B and Musante, Charles and Harmon, David and Sullivan, Timothy
2006 IEEE International Conference on IC Design and Technology, pp. 1--4
Abstract

Technology elements and chip design for low power applications
Hook, Terence B
2006 International Electron Devices Meeting, pp. 1--4
Abstract


2005

Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration
Hook, Terence B and Bolam, Ronald and Clark, William and Burnham, Jay and Rovedo, Nivo and Schutz, Laura
Microelectronics Reliability 45(1), 47--56, Elsevier, 2005
Abstract


2003

Lateral ion implant straggle and mask proximity effect
Hook, Terence B and Brown, J and Cottrell, Peter and Adler, Eric and Hoyniak, Dennis and Johnson, Jim and Mann, Randy
IEEE Transactions on Electron Devices 50(9), 1946--1951, 2003
Abstract

The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2 nm) Nitrided gate oxide
Hook, Terence B and Kontra, Richard and Burnham, Jay and Lavoie, Mark
Plasma-and Process-Induced Damage, 2003 8th International Symposium, pp. 150--153
Abstract

Ultralow-power SRAM technology
Mann, Randy W and Abadeer, WW and Breitwisch, Matthew J and Bula, O and Brown, Jeff S and Colwill, Bryant C and Cottrell, Peter E and Crocco, WT and Furkay, Stephen S and Hauser, Michael J and others
IBM Journal of Research and Development 47(5.6), 553--566, IBM, 2003
Abstract


2002

High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step
Hook, Terence B and Brown, Jeffery S and Breitwisch, Matthew and Hoyniak, Dennis and Mann, Randy
IEEE Transactions on Electron Devices 49(9), 1623--1627, IEEE, 2002
Abstract

Mechanism of threshold voltage shift ($Delta$Vth) caused by negative bias temperature instability (NBTI) in deep submicron pMOSFETs
Liu, Chuan-Hsi and Lee, Ming T and Lin, Chih-Yung and Chen, Jenkon and Loh, YT and Liou, Fu-Tai and Schruefer, Klaus and Katsetos, Anastasios A and Yang, Zhijian and Rovedo, Nivo and others
Japanese journal of applied physics 41(4S), 2423, IOP Publishing, 2002
Abstract

Noise margin and leakage in ultra-low leakage SRAM cell design
Hook, Terence B and Breitwisch, Matt and Brown, Jeff and Cottrell, P and Hoyniak, Dennis and Lam, Chung and Mann, Randy
IEEE Transactions on Electron Devices 49(8), 1499--1501, IEEE, 2002
Abstract


2001

Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation
Hook, Terence B and Harmon, David and Lin, Chuan
Microelectronics Reliability 41(5), 751--765, Elsevier, 2001
Abstract

The effects of fluorine on parametrics and reliability in a 0.18-$mu$m 3.5/6.8 nm dual gate oxide CMOS technology
Hook, Terence B and Adler, Eric and Guarin, Fernando and Lukaitis, Joseph and Rovedo, Nivo and Schruefer, Klaus
IEEE Transactions on Electron Devices 48(7), 1346--1353, IEEE, 2001
Abstract

Enchanced multi-threshold (MTCMOS) circuits using variable well bias
Kosonocky, Stephen V and Immediato, Mike and Cottrell, Peter and Hook, Terence and Mann, Randy and Brown, Jeff
Proceedings of the 2001 international symposium on Low power electronics and design, pp. 165--169
Abstract


2000

Dual gate oxide charging damage in damascene copper technologies
Stamper, Anthony K and Chou, Anthony and Hook, Terence B
Plasma Process-Induced Damage, 2000 5th International Symposium on, pp. 109--112
Abstract

A circuit model for evaluating plasma-induced charging damage in bulk and SOI technologies
Hook, Terence B and Chou, A and Khare, M and Mocuta, A
Plasma Process-Induced Damage, 2000 5th International Symposium on, pp. 30--33
Abstract

Detection of thin oxide (3.5 nm) dielectric degradation due to charging damage by rapid-ramp breakdown
Hook, Terence B and Harmon, David and Lin, Chuan
Reliability Physics Symposium, 2000. Proceedings. 38th Annual 2000 IEEE International, pp. 377--388
Abstract


1999

Process-induced damage in a dual-oxide (3.5/6.8 nm) 0.18-$mu$m copper CMOS technology
Hook, Terence B
Plasma Process-Induced Damage, 1999 4th International Symposium on, pp. 181--183
Abstract

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations
Hook, Terence B and Burnham, Jay S and Bolam, Ronald J
IBM journal of research and development 43(3), 393--406, IBM, 1999
Abstract


1998

Backside films and charging during via etch in LOCOS and STI technologies
Hook, Terence B
Plasma Process-Induced Damage, 1998 3rd International Symposium on, pp. 11--14
Abstract


1997

Resistive extraction of polysilicon gate linewidth
Miles, Glen and Hook, Terence and Faucher, Margaret and Morrett, Kent
Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI, pp. 24--29
Abstract


1993

Yield Improvement for a 3.5-ns BICMOS Technology in a 200-mm Manufacturing Line
Chen, Bomy and Hook, Terence and Starkey, Gordon and Bhattacharyya, Arup and Faucher, Margaret and Racine, Carol and Willets, Christa and Eslinger, Steven and Kulkarni, Subhash and King, William and others
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on, pp. 301--305
Abstract


1992

Automatic extraction of circuit models from layout artwork for a BiCMOS technology
Hook, Terence B
IEEE transactions on computer-aided design of integrated circuits and systems 11(6), 732--738, IEEE, 1992
Abstract


1990

An analytical formulation of the peripheral base resistance with application to statistical process variations
Hook, Terence B
Solid-State Electronics 33(10), 1319--1326, Elsevier, 1990
Abstract


1987

Electron trapping during high-field tunneling injection in metal-oxide-silicon capacitors: The effect of gate-induced strain
Hook, Terence B and Ma, T-P
Journal of applied physics 62(3), 931--938, AIP Publishing, 1987
Abstract

The effect of aluminum vs. photoresist masking on the etching rates of silicon and silicon dioxide in CF 4/O 2 plasmas
Fedynyshyn, Theodore H and Grynkewich, Gregory W and Hook, Terence B and Liu, Ming-Deng and Ma, Tso-Ping
Journal of the Electrochemical Society 134(1), 206--209, The Electrochemical Society, 1987
Abstract


1986

High-field tunneling calculations in metal-oxide-silicon capacitors incorporating the perimeter effect
Hook, Terence B and Ma, T-P
Journal of applied physics 59(11), 3881--3889, AIP Publishing, 1986
Abstract

Hot-electron induced interface traps in metal/SiO2/Si capacitors: The effect of gate-induced strain
Hook, Terence B and Ma, TP
Applied physics letters 48(18), 1208--1210, AIP Publishing, 1986
Abstract


1985

Perimeter-related current in high-field tunneling into SiO2
Hook, Terence B and Ma, TP
Applied Physics Letters 47(4), 417--419, AIP Publishing, 1985
Abstract


Year Unknown

Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations
Lu, Darsen and Morin, Pierre and Sahu, Bhagawan and Hook, Terence B and Hashemi, Pouya and Scholze, Andreas and Kim, Bomsoo and Kerber, Pranita and Khakifirooz, Ali and Oldiges, Phil and others
researchgate.net, 0
Abstract




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