Terence B. (Terry) Hook  Terence B. (Terry) Hook photo       

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logic device design
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2016

Extra gate device for nanosheet
Doris, Bruce B and Hook, Terence B and Wang, Junli
US Patent 9,490,335
Abstract

Series-connected nanowire structures
Gauthier Jr, Robert J and Hook, Terence B and Mitra, Souvick
US Patent 9,431,388
Abstract

FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
Hook, Terence B and Mendez, Horacio
US Patent 20,160,079,127
Abstract

Immunity to inline charging damage in circuit designs
Henderson, Zachary and Hibbeler, Jason D and Hook, Terence B and Palmer, Nicholas and Peterson, Kirk D
US Patent 9,378,329
Abstract

FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
Hook, Terence B and Mendez, Horacio
US Patent 20,160,079,277
Abstract


2015

Partial FIN on oxide for improved electrical isolation of raised active regions
Cheng, Kangguo and Harley, Eric C and Hook, Terence B and Khakifirooz, Ali and Utomo, Henry K and Vega, Reinaldo A
US Patent 9,219,114
Abstract

Establishing a thermal profile across a semiconductor chip
Hook, Terence B and Schnabel, Christopher M and Sherony, Melanie J
US Patent 9,178,495
Abstract

Low gate-to-drain capacitance fully merged finFET
Hook, Terence B and Nowak, Edward J
US Patent 9,171,952
Abstract

Estimating transistor characteristics and tolerances for compact modeling
Hook, Terence B and Johnson, Jeffrey B
US Patent 9,009,638
Abstract

Modeling charge distribution on FinFET sidewalls
Agarwal, Samarth and Bajaj, Mohit and Hook, Terence B
US Patent 9,064,976
Abstract

Semiconductor device including ESD protection device
Yamashita, Tenko and Hook, Terence B and Basker, Veeraraghavan S and Yeh, Chun-Chen
US Patent 9,012,997
Abstract

In-situ relaxation for improved CMOS product lifetime
Hook, Terence B and Sherony, Melanie J and Schnabel, Christopher M
US Patent 9,059,120
Abstract

Electrostatic discharge resistant diodes
Bu, Huiming and Gauthier Jr, Robert J and Hook, Terence B and Leobandung, Effendi and Yamashita, Tenko
US Patent 9,064,885
Abstract

Method for dynamically switching analyses and for dynamically switching models in circuit simulators
Olsen, Michael Claus and Deng, Jie and Hook, Terence B and Nutakki, Madan Mohan Naga
US Patent 8,959,008
Abstract

In-situ annealing for extending the lifetime of CMOS products
Hook, Terence B and Sherony, Melanie J and Schnabel, Christopher M
US Patent 9,064,824
Abstract


2014

Method of making heat sink for integrated circuit devices
Coolbaugh, Douglas D and Eshun, Ebenezer E and Hook, Terence B and Rassel, Robert M and Sprogis, Edmund J and Stamper, Anthony K and Murphy, William J
US Patent 8,881,379
Abstract

Static noise margin monitoring circuit and method
Cranford Jr, Hayden C and Hook, Terence B
US Patent 8,729,908
Abstract

Integrated circuit including DRAM and SRAM/logic
Cheng, Kangguo and Doris, Bruce B and Hook, Terence B and Khakifirooz, Ali and Kulkarni, Pranita
US Patent 8,653,596
Abstract


2013

Pseudo butted junction structure for back plane connection
Hook, Terence B
US Patent 8,513,106
Abstract

Transistors having multiple lateral channel dimensions
Bu, Huiming and Hook, Terence B and Leobandung, Effendi and Standaert, Theodorus E
US Patent App. 14/088,480
Abstract

Method and structure for balancing power and performance using fluorine and nitrogen doped substrates
Anderson, Brent A and Hook, Terence B
US Patent 8,431,955
Abstract

Self-limiting oxygen seal for high-K dielectric and design structure
Hook, Terence B and Narayanan, Vijay and Shah, Jay M and Sherony, Melanie J and Stein, Kenneth J and Wang, Helen H and Zhu, Chendong
US Patent 8,564,074
Abstract

Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip
Cranford Jr, Hayden C and Hook, Terence B
US Patent 8,416,009
Abstract

Physically unclonable function implemented through threshold voltage comparison
Ficke, Joel T and Hall, William E and Hook, Terence B and Sperling, Michael A and Wissel, Larry
US Patent 8,619,979
Abstract

Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability
Dennard, Robert H and Hook, Terence B
US Patent 8,552,500
Abstract

Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range
Hook, Terence B and Johnson, Jeffrey B
US Patent 8,407,656
Abstract


2012

Method of cooling a resistor
Coolbaugh, Douglas D and Eshun, Ebenezer E and Hook, Terence B and Rassel, Robert M and Sprogis, Edmund J and Stamper, Anthony K and Murphy, William J
US Patent 8,230,586
Abstract

Field effect transistor devices with recessed gates
Bu, Huiming and Hook, Terence B and Vega, Reinaldo A
US Patent App. 13/596,409
Abstract


2011

Design method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range
Hook, Terence B and Johnson, Jeffrey B
US Patent App. 13/167,826
Abstract

Design method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range
Hook, Terence B and Johnson, Jeffrey B
US Patent App. 13/167,826
Abstract

Isolated high performance FET with a controllable body resistance
Hook, Terence B and Hu, Jenny and Park, Jae-Eun
US Patent 7,939,894
Abstract

Methods and Structures Involving Terminal Connections
Hook, Terence B and Ramachandran, Vidhya
US Patent App. 12/984,640
Abstract

Method of providing protection against charging damage in hybrid orientation transistors
Hook, Terence B and Mocuta, Anda C and Sleight, Jeffrey W and Stamper, Anthony K
US Patent 7,879,650
Abstract

Method and structure to protect FETs from plasma damage during FEOL processing
Nair, Deleep R and Hook, Terence B
US Patent 7,863,112
Abstract

Trench isolation and method of fabricating trench isolation
Hook, Terence Blackwell and Johnson, Jeffrey Bowman and Nakos, James Spiros
US Patent 8,012,848
Abstract

Heat sink for integrated circuit devices
Coolbaugh, Douglas D and Eshun, Ebenezer E and Hook, Terence B and Rassel, Robert M and Sprogis, Edmund J and Stamper, Anthony K and Murphy, William J
US Patent 7,994,895
Abstract


2010

Determining allowance antenna area as function of total gate insulator area for SOI technology
Bonges, Henry A and Hook, Terence B and Pokorny, William F and Zimmerman, Jeffrey S
US Patent 7,712,057
Abstract

Method of determining n-well scattering effects on FETs
Galland, Micah and Hook, Terence B
US Patent 7,824,933
Abstract

Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
Chapple-Sokol, Jonathan D and Hook, Terence B and Li, Baozhen and McDevitt, Thomas L and Ponsolle, Christopher A and Reuter, Bette B and Sullivan, Timothy D and Zimmerman, Jeffrey S
US Patent 7,649,262
Abstract

Method of selectively adjusting ion implantation dose on semiconductor devices
Hook, Terence B and Leake, Gerald and others
US Patent 7,682,910
Abstract

Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same
Booth Jr, Roger Allen and Cheng, Kangguo and Hook, Terence B
US Patent 7,785,979
Abstract


2009

Protection against charging damage in hybrid orientation transistors
Hook, Terence B and Mocuta, Anda C and Sleight, Jeffrey W and Stamper, Anthony K
US Patent 7,492,016
Abstract

Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage
Hook, Terence B and Zimmerman, Jeffrey Scott
US Patent 7,560,345
Abstract

Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices
Anderson, Brent A and Hook, Terence B
US Patent 7,615,827
Abstract

Methods of improving operational parameters of pair of matched transistors and set of transistors
Hook, Terence B and Johnson, Jeffrey B and Lee, Yoo-Mi
US Patent 7,516,426
Abstract


2007

Immunity to charging damage in silicon-on-insulator devices
Eng, Chung-Ping and Hook, Terence B and Zimmerman, Jeffrey S
US Patent App. 11/869,176
Abstract

Structure and method for providing precision passive elements
Coolbaugh, Douglas D and Cranford Jr, Hayden C and Hook, Terence B and Stamper, Anthony K
US Patent 7,300,807
Abstract

Device modeling for proximity effects
Adler, Eric and Biesemans, Serge and Galland, Micah S and Hook, Terence B and McCullen, Judith H and Phipps, Eric S and Slinkman, James A
US Patent 7,302,376
Abstract

Structure and method for local resistor element in integrated circuit technology
Gill, Jason P and Hook, Terence B and Mann, Randy W and Murphy, William J and Tonti, William R and Voldman, Steven H
US Patent 7,166,904
Abstract


2006

Structure and method for reducing susceptibility to charging damage in soi designs
Eng, Chung-Ping and Bonges, Henry A and Zimmerman, Jeffrey S and Hook, Terence B
US Patent App. 11/383,565
Abstract

Highly tunable metal-on-semiconductor varactor
Hook, Terence B and Park, Jae-Eun
US Patent App. 11/617,322
Abstract

Dual gate dielectric thickness devices
Anderson, Brent A and Hook, Terence B
US Patent 7,087,470
Abstract

Low trigger voltage, low leakage ESD NFET
Chatty, Kiran V and Gauthier, Robert J and Hook, Terence B and Putnam, Christopher S and Muhammad, Mujahid
US Patent 7,098,513
Abstract

Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
Bonges III, Henry A and Harmon, David L and Hook, Terence B and Lai, Wing L
US Patent 7,067,886
Abstract

CMOS well structure and method of forming the same
Haensch, Wilfried and Hook, Terence B and Hsu, Louis C and Joshi, Rajiv V and Rausch, Werner
US Patent 7,132,323
Abstract


2005

Selective silicide blocking
Breitwisch, Matthew J and Brown, Jeffrey S and Hook, Terence B and Mann, Randy W and Putnam, Christopher S and Younus, Mohammad I
US Patent 6,881,672
Abstract

Leakage compensation circuit
Bernstein, Kerry and Bonaccio, Anthony R and Fifield, John A and Haar, Allen P and Ho, Shiu C and Hook, Terence B and Soma, Michael A and Wyatt, Stephen D
US Patent 6,956,417
Abstract


2004

Method for forming a retrograde implant
Brown, Jeffrey S and Colwill, Bryant C and Hook, Terence B and Hoyniak, Dennis
US Patent 6,797,592
Abstract

On chip resistor calibration structure and method
Hook, Terence B and Singh, Raminderpal and Wyatt, Stephen D
US Patent 6,825,490
Abstract

Selective silicide blocking
Breitwisch, Matthew J and Brown, Jeffrey S and Hook, Terence B and Mann, Randy W and Putnam, Christopher S and Younus, Mohammad I
US Patent 6,700,163
Abstract


2003

Composite transistor having a slew-rate control
Bernstein, Kerry and Correale Jr, Anthony and Hook, Terence Blackwell and Stout, Douglas Willard
US Patent 6,670,683
Abstract

Method for forming a retrograde implant
Brown, Jeffrey S and Colwill, Bryant C and Hook, Terence B and Hoyniak, Dennis
US Patent 6,610,585
Abstract


2002

Silicide block bounded device
Ballantine, Arne W and Hook, Terence B
US Patent 6,339,018
Abstract

Angled implant process
Hook, Terence B and Mann, Randy W
US Patent 6,489,223
Abstract


2001

Apparatus and method for detecting defective NVRAM cells
Hook, Terence B and Lam, Chung H and Lee, Eric S and Nakos, James S and Rovedo, Nivo and Williams, Richard Q and Wong, Robert C
US Patent 6,256,755
Abstract

Method of detecting electromagnetic radiation with bandgap engineered active pixel cell design
Hook, Terence B and Johnson, Jeffrey B and Leidy, Robert and Wong, Hon-Sum P
US Patent 6,278,102
Abstract

Asymmetrical field effect transistor
Hook, Terence B and Hoyniak, Dennis and Nowak, Edward J
US Patent 6,271,565
Abstract

Structures and methods to minimize plasma charging damage in silicon on insulator devices
Khare, Mukesh and Agnello, Paul and Chou, Anthony and Hook, Terence and Mocuta, Anda
US Patent App. 09/822,453
Abstract

High performance semiconductor memory device with low power consumption
Andersen, John E and Hook, Terence B and Hsu, Louis L and Hwang, Wei and Kosonocky, Stephen V and Wang, Li-Kong
US Patent 6,307,805
Abstract

Method of forming a complementary active pixel sensor cell
Hook, Terence B and Johnson, Jeffrey B and Wong, Hon-Sum P
US Patent 6,194,702
Abstract

Switched body SOI (silicon on insulator) circuits and fabrication method therefor
Bertin, Claude Louis and Ellis-Monaghan, John Joseph and Hedberg, Erik Leigh and Hook, Terence Blackwell and Mandelman, Jack Allan and Nowak, Edward Joseph and Pricer, Wilbur David and Tong, Minh Ho and Tonti, William Robert
US Patent 6,239,649
Abstract


2000

NVRAM utilizing high voltage TFT device and method for making the same
Hook, Terence B and Nakos, James S and Williams, Richard Q
US Patent 6,022,770
Abstract

Active pixel sensor cell and method of using
Hook, Terence B and Johnson, Jeffrey B and Wong, Hon-Sum P
US Patent 6,026,964
Abstract

Method to perform selective drain engineering with a non-critical mask
Hook, Terence B and Hoyniak, Dennis and Nowak, Edward J
US Patent 6,083,794
Abstract


1999

Semiconductor transistor with multi-depth source drain
Ballantine, Arne Watson and Gehres, Rainer Ernst and Hook, Terence Blackwell and Smeys, Peter
US Patent App. 09/363,355
Abstract

Hot electron compensation for improved MOS transistor reliability
Forhan, Timothy E and Hook, Terence B and Mittl, Steven W and Nowak, Edward J and Sayala, Madhu and Warren, Ronald A
US Patent 5,982,225
Abstract

Dual EPI active pixel cell design and method of making the same
Hook, Terence B and Wong, Hon-Sum P
US Patent 5,898,196
Abstract

Use of deuterated materials in semiconductor processing
Clark, William F and Ference, Thomas G and Hook, Terence B and Martin, Dale W
US Patent 5,972,765
Abstract


1996

Semiconductor manufacturing process for low dislocation defects
Chen, Bomy A and Hook, Terence B and Kulkarni, Subhash B
US Patent 5,562,770
Abstract




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