Vijay Narayanan  Vijay Narayanan photo       

contact information

Manager and Distinguished Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE   |  Materials Research Society (MRS)


2016

(Invited) CMOS Compatible High Performance IIIV Devices: Opportunities and Challenges
Sun, Yanning and Shiu, Kuen-Ting and Cheng, Cheng-Wei and Majumdar, Amlan and Bruce, Robert and Yau, Jeng-bang and Farmer, Damon and Zhu, Yu and Hopstaken, Marinus and Frank, Martin M and others
ECS Transactions 72(4), 313--319, The Electrochemical Society, 2016


2015

An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
Miao, Xin and Bao, Ruqiang and Kwon, Unoh and Wong, Keith and Rausch, Werner and Weng, Weihao and Wachnik, Richard and Grunow, Stephan and Narayanan, Vijay and Li, Xiuling and others
IEEE Electron Device Letters 36(4), 384--386, IEEE, 2015

Evolution of interfacial Fermi level in In0. 53Ga0. 47As/high-$kappa$/TiN gate stacks
Carr, Adra and Rozen, John and Frank, Martin M and Ando, Takashi and Cartier, Eduard A and Kerber, Pranita and Narayanan, Vijay and Haight, Richard
Applied Physics Letters 107(1), 012103, AIP Publishing, 2015

High-mobility High-Ge-Content Si 1- x Ge x-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x~ 0.7, scaled EOT~ 8.5{AA} and~ 10nm fin width
Hashemi, P and Ando, T and Balakrishnan, K and Bruley, J and Engelmann, S and Ott, JA and Narayanan, V and Park, D-G and Mo, RT and Leobandung, E
VLSI Technology (VLSI Technology), 2015 Symposium on, pp. T16--T17


2014

CMOS-Compatible Self-Aligned In 0.53 Ga 0.47 As MOSFETs With Gate Lengths Down to 30 nm
Majumdar, Amlan and Sun, Yanning and Cheng, Cheng-Wei and Kim, Young-Hee and Rana, Uzma and Martin, Ryan M and Bruce, Robert L and Shiu, Kuen-Ting and Zhu, Yu and Farmer, Damon B and others
IEEE Transactions on Electron Devices 61(10), 3399--3404, IEEE, 2014

High performance 14nm SOI FinFET CMOS technology with 0.0174$mu$m 2 embedded DRAM and 15 levels of Cu metallization
Lin, CH and Greene, B and Narasimha, S and Cai, J and Bryant, A and Radens, C and Narayanan, V and Linder, B and Ho, H and Aiyar, A and others
2014 IEEE International Electron Devices Meeting, pp. 3--8

Incorporation of La in epitaxial SrTiO3 thin films grown by atomic layer deposition on SrTiO3-buffered Si (001) substrates
McDaniel, Martin D and Posadas, Agham and Ngo, Thong Q and Karako, Christine M and Bruley, John and Frank, Martin M and Narayanan, Vijay and Demkov, Alexander A and Ekerdt, John G
Journal of Applied Physics 115(22), 224108, AIP Publishing, 2014

Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond
T Ando, B Kannan, U Kwon, WL Lai, BP Linder, EA Cartier, R Haight, M Copel, J Bruley, SA Krishnan, others
VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on, pp. 1--2

Effect of I/O oxide process optimization on the nbti dependence of T inv scaling for a 20 nm bulk planar Replacement Gate process
CE Tian, G La Rosa, W Liu, M Jin, WL Lai, S Siddiqui, F Guarin, H Kothari, W McMahon, S Uppal, others
Reliability Physics Symposium, 2014 IEEE International, pp. PI--3

Tunable electrical properties of TaNx thin films grown by ionized physical vapor deposition
Miri Choi, Catherine Dubourdieu, Andrew J Kellock, Kam Leung Lee, Richard A Haight, Adam Pyzyna, Martin M Frank, Alexander A Demkov, Vijay Narayanan
Journal of Vacuum Science \& Technology B 32(5), 051202, AVS: Science \& Technology of Materials, Interfaces, and Processing, 2014

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs
Martin M Frank, Yu Zhu, Stephen W Bedell, Takashi Ando, Vijay Narayanan
ECS Transactions 61(2), 213--223, The Electrochemical Society, 2014

The Quantum Metal Ferroelectric Field-Effect Transistor
David J Frank, Paul M Solomon, Catherine Dubourdieu, Martin M Frank, Vijay Narayanan, Thomas N Theis
2014 - ieeexplore.ieee.org, IEEE


2013

2 nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
Ortolland, C and Jaeger, D and Mcardle, TJ and Dewan, C and Robison, RR and Zhao, K and Cai, J and Chang, P and Liu, Y and Varadarajan, V and others
2013 IEEE International Electron Devices Meeting, pp. 9--4

Impact of hydrogen in capping layers on BTI degradation and recovery in high-$\kappa$ replacement metal gate transistors
M Jin, CE Tian, G La Rosa, S Uppal, W Mcmahon, H Kothari, Y Liu, E Cartier, WL Lai, A Dasgupta, others
Reliability Physics Symposium (IRPS), 2013 IEEE International, pp. PI--3

NFET effective work function improvement via stress memorization technique in replacement metal gate technology
Y Liu, HV Meer, O Gluschenkov, X Yang, F Sato, KH Cho, M Ganz, H Utomo, Y Wang, U Kwon, others
VLSI Technology (VLSIT), 2013 Symposium on, pp. T198--T199

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal--oxide--semiconductor devices
RK Pandey, Rajesh Sathiyanarayanan, Unoh Kwon, Vijay Narayanan, KVRM Murali
Journal of Applied Physics 114(3), 034505, AIP Publishing, 2013

(Invited) The Past, Present and Future of High-k/Metal Gates
Kisik Choi, Takashi Ando, Eduard A Cartier, Andreas Kerber, Vamsi Paruchuri, John Iacoponi, Vijay Narayanan
ECS Transactions 53(3), 17--26, The Electrochemical Society, 2013

Origins of Effective Work Function Roll-Off Behavior for High-k Last Replacement Metal Gate Stacks
Takashi Ando, Eduard A Cartier, John Bruley, Kisik Choi, Vijay Narayanan
2013 - ieeexplore.ieee.org, IEEE

Aggressive SiGe channel gate stack scaling by remote oxygen scavenging: Gate-first pFET performance and reliability
Martin M. Frank, Eduard A. Cartier, Takashi Ando, Stephen W. Bedell, John Bruley, Yu Zhu, Vijay Narayanan
ECS Solid State Lett. 2(2), N8-N10, The Electrochemical Society, 2013

Deposited ALD SiO2 High-k/Metal Gate Interface for High Voltage Analog and I/O Devices on Next Generation Alternative Channels and FINFET Device Structures
Shahab Siddiqui, Murshed M Chowdhury, Maryjane Brodsky, Nilufa Rahim, Min Dai, Siddarth Krishnan, Steve Fugardi, Ernest Wu, Anthony Chou, Shreesh Narasimha, others
ECS Transactions 53(3), 137--146, The Electrochemical Society, 2013

Process and local layout effect interaction on a high performance planar 20nm CMOS
F Sato, R Ramachandran, H Van Meer, KH Cho, A Ozbek, X Yang, Y Liu, Z Li, X Wu, S Jain, others
VLSI Technology (VLSIT), 2013 Symposium on, pp. T116--T117

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness
Min Dai, Yanfeng Wang, Joseph Shepard, Jinping Liu, Maryjane Brodsky, Shahab Siddiqui, Paul Ronsheim, Dimitris P Ioannou, Chandra Reddy, William Henson, others
Journal of Applied Physics 113(4), 044103, AIP Publishing, 2013

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
W McMahon, C Tian, S Uppal, H Kothari, M Jin, G LaRosa, T Nigam, A Kerber, BP Linder, E Cartier, others
Reliability Physics Symposium (IRPS), 2013 IEEE International, pp. 4C--4

Characterization and optimization of charge trapping in high-k dielectrics
Eduard Cartier, Takashi Ando, Marinus Hopstaken, Vijay Narayanan, Rishikesh Krishnan, JF Shepard, Michael D Sullivan, Siddarth Krishnan, Michael P Chudzik, Sandip De, others
Reliability Physics Symposium (IRPS), 2013 IEEE International, pp. 5A--2

Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode
Catherine Dubourdieu, John Bruley, Thomas M Arruda, Agham Posadas, Jean Jordan-Sweet, Martin M Frank, Eduard Cartier, David J Frank, Sergei V Kalinin, Alexander A Demkov, others
Nature nanotechnology 8(10), 748--754, Nature Publishing Group, 2013


2012

Bias temperature instability in High-$kappa$/metal gate transistors-Gate stack scaling trends
Krishnan, Siddarth and Narayanan, Vijay and Cartier, Eduard and Ioannou, Dimitris and Zhao, Kai and Ando, Takashi and Kwon, Unoh and Linder, Barry and Stathis, James and Chudzik, Michael and others
Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 5A--1

Physical characterization of sub-32-nm semiconductor materials and processes using advanced ion beam-based analytical techniques
MJP Hopstaken, D. Pfeiffer, M. Copel, MS Gordon, T. Ando, V. Narayanan, H. Jagannathan, S. Molis, JA Wahl, H. Bu, D.K. Sadana, L. Czornomaz, C. Marchiori, J. Fompeyrine
Surface and Interface Analysis 45(1), 338-344, Wiley Online Library, 2012

A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
U Kwon, K Wong, SA Krishnan, L Econimikos, X Zhang, C Ortolland, LD Thanh, J Laloe, JY Huang, LF Edge, others
VLSI Technology (VLSIT), 2012 Symposium on, pp. 29--30

High performance bulk planar 20nm CMOS technology for low power mobile applications
Hulling Shang, S Jain, E Josse, E Alptekin, MH Nam, SW Kim, KH Cho, I Kim, Y Liu, X Yang, others
VLSI Technology (VLSIT), 2012 Symposium on, pp. 129--130

Aggressive SiGe Channel Gate Stack Scaling by Remote Oxygen Scavenging: pFET Performance and Reliability
Martin M. Frank, Eduard A. Cartier, Takashi Ando, Stephen W. Bedell, John Bruley, Yu Zhu, Vijay Narayanan
222nd ECS Meeting, pp. 2615, 2012

Bias temperature instability in High-$\kappa$/metal gate transistors-Gate stack scaling trends
Siddarth Krishnan, Vijay Narayanan, Eduard Cartier, Dimitris Ioannou, Kai Zhao, Takashi Ando, Unoh Kwon, Barry Linder, James Stathis, Michael Chudzik, others
Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 5A--1


2011

Characterization of Strontium Oxide Layers on Silicon for CMOS High-K Gate Stack Scaling
J. Bruley, M. Frank, C. Marchiori, J. Fompeyrine, V. Narayanan
Microscopy and Microanalysis 17(S2), 1350-1351, Cambridge Univ Press, 2011

A 0.021 $\mu$m 2 trigate SRAM cell with aggressively scaled gate and contact pitch
MA Guillorn, J Chang, A Pyzyna, S Engelmann, M Glodde, E Joseph, R Bruce, JA Ott, A Majumdar, F Liu, others
VLSI Technology (VLSIT), 2011 Symposium on, pp. 64--65

Epitaxial SrO interfacial layers for HfO2-Si gate stack scaling
C. Marchiori, MM Frank, J. Bruley, V. Narayanan, J. Fompeyrine
Applied Physics Letters 98(5), 052908-052908, 2011


ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08$\mu$m 2 SRAM cell
K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, B Haran, A Kumar, T Adam, A Reznicek, N Loubet, H He, others
VLSI Technology (VLSIT), 2011 Symposium on, pp. 128--129

Millisecond Flash Annealing as a Flatband Voltage Shift Enabler for p-Type Metal-Oxide-Semiconductor Devices with High-k/Metal Gate
Changhwan Choi, Vijay Narayanan
Electrochemical and Solid-State Letters 14(6), H241--H243, The Electrochemical Society, 2011

Full metal gate with borderless contact for 14 nm and beyond
S-C Seo, LF Edge, S Kanakasabapathy, M Frank, A Inada, L Adam, MM Wang, K Watanabe, P Jamison, K Ariyoshi, others
VLSI Technology (VLSIT), 2011 Symposium on, pp. 36--37

(Invited) Voltage Ramp Stress Based Stress-And-Sense Test Method For Reliability Characterization of Hf-Base High-k/Metal Gate Stacks For CMOS Technologies
Eduard Cartier, Adreas Kerber, Siddarth Krishnan, Barry Linder, Takashi Ando, Martin M Frank, Kisik Choi, Vijay Narayanan
ECS Transactions 41(3), 337--348, The Electrochemical Society, 2011

Origin of Effective Work Function Roll-off Behavior for Replacement Gate Process Studied by Low-temperature Interfacial Layer Scavenging Technique
Takashi Ando, Eduard Cartier, John Bruley, Kisik Choi, and Vijay Narayanan
42nd IEEE Semiconductor Interface Specialists Conference, pp. 1-2, 2011

High temperature (1000° C) compatible Y--La--Si--O silicate gate dielectric in direct contact with Si with 7.7 \AA equivalent oxide thickness
C Dubourdieu, E Cartier, J Bruley, M Hopstaken, MM Frank, V Narayanan
Applied Physics Letters 98(25), 252901, AIP Publishing, 2011

A Manufacturable Dual Channel (Si and SiGe) High-K Metal Gate CMOS Technology with Multiple Oxides for High Performance and Low Power Applications
S. Krishnan, U. Kwon, N. Moumen, M. Stoker, E. C. Harley, S. W. Bedell, D. R. Nair, B. J. Greene, W. K. Henson, M. M. Chowdhury, D. P. Prakash, E. Wu, D. P. Ioannou, E. Cartier, M.-h. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Har
International Electron Devices Meeting, pp. 28-1, 2011

Fundamental aspects of HfO 2-based high-k metal gate stack reliability and implications on t inv-scaling
E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, K Zhao, F Monsieur, J Stathis, others
Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 18--4

Ruthenium based metals using atomic vapor deposition for gate electrode applications
C. Choi, T. Ando, and V. Narayanan
Applied Physics Letters98, 083506, 2011

Impact of diffusionless anneal using dynamic surface anneal on the electrical properties of a high-k/metal gate stack in metal-oxide-semiconductor devices
C. Choi, K-L Lee, and V. Narayanan
Appl. Phys. Lett.98, 123506, 2011

Maximized Benefit of La--Al--O Higher-$ k $ Gate Dielectrics by Optimizing the La/Al Atomic Ratio
H Arimura, S L Brown, A Callegari, A Kellock, J Bruley, M Copel, H Watanabe, V Narayanan, T Ando
Electron Device Letters, IEEE 32(3), 288--290, IEEE, 2011


Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling
M M Frank, C Marchiori, J Bruley, J Fompeyrine, V Narayanan
Microelectronic Engineering, Elsevier, 2011


2010

Structure and composition of metal-doped HfO2 gate oxides in CMOS devices studied by high resolution STEM and EELS
J Bruley, MM Frank, V Narayanan, B Mendis, M Gass
Microscopy and Microanalysis 16(S2), 1892--1893, Cambridge Univ Press, 2010

High-/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
Marwan H Khater, Zhen Zhang, Jin Cai, Christian Lavoie, Christopher D'Emic, Qingyun Yang, Bin Yang, Michael Guillorn, David Klaus, John A Ott, others
Electron Device Letters, IEEE 31(4), 275--277, IEEE, 2010

Methodology of ALD HfO2 High-$\kappa$ gate dielectric optimization by cyclic depositions and anneals
Hemanth Jagannathan, Robert D Clark, Steve Consiglio, Paul Jamison, Barry Linder, Marinus Hopstaken, Gert Leusink, Vamsi Paruchuri, Vijay Narayanan
ECS Transactions 33(3), 157--164, The Electrochemical Society, 2010

Optimizing Band-Edge High-$\kappa$/Metal Gate n-MOSFETs with ALD Lanthanum Oxide Cap Layers: Oxidant and Positioning Effects
Robert D Clark, Hemanth Jagannathan, Steve Consiglio, Paul Jamison, Cory Wajda, Lisa Edge, Vamsi Paruchuri, Vijay Narayanan, Gert Leusink
ECS Transactions 33(3), 75--81, The Electrochemical Society, 2010

Oxygen Transport in High-k Metal Gate Stacks and Physical Characterization by SIMS Using Isotopic Labeled Oxygen
M J Hopstaken, J Bruley, D Pfeiffer, M Copel, M M Frank, E Cartier, T Ando, V Narayanan
ECS Trans. 28(1), 105, The Electrochemical Society, 2010

Ultimate EOT Scaling (< 5A\aa) Using Hf-Based High-$\kappa$ Gate Dielectrics and Impact on Carrier Mobility
Takashi Ando, Martin M Frank, Kisik Choi, Changhwan Choi, John Bruley, Marinus Hopstaken, Matthew Copel, Richard Haight, Hiroaki Arimura, Heiji Watanabe, others
Meeting Abstracts, pp. 927--927, 2010

(Invited) Ultimate EOT Scaling (< 5A\aa) Using Hf-Based High-$\kappa$ Gate Dielectrics and Impact on Carrier Mobility
Takashi Ando, Martin M Frank, Kisik Choi, Changhwan Choi, John Bruley, Marinus J Hopstaken, Richard Haight, Matthew Copel, Hiroaki Arimura, Heiji Watanabe, others
ECS Transactions 28(1), 115--123, The Electrochemical Society, 2010

Oxygen migration in TiO2-based higher-k gate stacks
SangBum Kim, Stephen L Brown, Stephen M Rossnagel, John Bruley, Matthew Copel, Marco JP Hopstaken, Vijay Narayanan, Martin M Frank
Journal of Applied Physics 107(5), 054102, AIP Publishing, 2010

Physical origins of mobility degradation in extremely scaled SiO/HfO gate stacks with La and Al induced dipoles
Takashi Ando, Matt Copel, John Bruley, Martin M Frank, Heiji Watanabe, Vijay Narayanan
Applied Physics Letters96, 132904, 2010


Temperature-dependent La-and Al-induced dipole behavior monitored by femtosecond pump/probe photoelectron spectroscopy
H Arimura, R Haight, S L Brown, A Kellock, A Callegari, M Copel, H Watanabe, V Narayanan, T Ando
Applied Physics Letters96, 132902, 2010


2009

Engineering Band-Edge High-$\kappa$/Metal Gate n-MOSFETs with Cap Layers Containing Group IIA and IIIB Elements by Atomic Layer Deposition
Hemanth Jagannathan, Lisa F Edge, Paul Jamison, Ryosuke Iijima, Vijay Narayanan, Vamsi K Paruchuri, Robert Clark, Steven Consiglio, Cory Wajda, Gert Leusink
ECS Transactions 19(1), 253--261, The Electrochemical Society, 2009

Interaction of La 2 O 3 capping layers with HfO 2 gate dielectrics
M Copel, S Guha, N Bojarczuk, E Cartier, V Narayanan, V Paruchuri
Applied Physics Letters 95(21), 212903--212903, AIP, 2009

Interfacial layer optimization of high-< i> k/metal gate stacks for low temperature processing
Barry P Linder, Vijay Narayanan, Eduard A Cartier
Microelectronic Engineering 86(7), 1632--1634, Elsevier, 2009

VLSI Tech
K Choi, H Jagannathan, C Choi, L Edge, T Ando, M Frank, P Jamison, M Wang, E Cartier, S Zafar, others
2009 - Dig, Dig

Scaling the MOSFET gate dielectric: From high-< i> k to higher-< i> k?
Martin M Frank, SangBum Kim, Stephen L Brown, John Bruley, Matthew Copel, Marco Hopstaken, Michael Chudzik, Vijay Narayanan
Microelectronic Engineering 86(7), 1603--1608, Elsevier, 2009

Interaction of La2O3 capping layers with HfO2 gate dielectrics
M. Copel, S. Guha, N. Bojarczuk, E. Cartier, V. Narayanan, and V. Paruchuri
Appl. Phys. Lett.95, 212903, 2009

High-$\kappa$/metal gate low power bulk technology-Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
D G Park, K Stein, K Schruefer, Y Lee, J P Han, W Li, H Yin, C Pacha, N Kim, M Ostermayr, others
VLSI Technology, Systems, and Applications, 2009, pp. 90--92

Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process
T Ando, MM Frank, K Choi, C Choi, J Bruley, M Hopstaken, M Copel, E Cartier, A Kerber, A Callegari, others
Electron Devices Meeting (IEDM), 2009 IEEE International, pp. 1--4

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes
C Choi, T Ando, E Cartier, M M Frank, R Iijima, V Narayanan
Microelectronic Engineering 86(7-9), 1737--1739, Elsevier, 2009

pFET Vt control with HfO2/TiN/poly-Si gate stack using a lateral oxygenation process
E Cartier, M Steen, BP Linder, T Ando, R Iijima, M Frank, JS Newbury, YH Kim, FR McFeely, M Copel, others
VLSI Technology, 2009 Symposium on, pp. 42--43

Scaling the MOSFET gate dielectric: From high-k to higher-k?(Invited Paper)
M M Frank, S B Kim, S L Brown, J Bruley, M Copel, M Hopstaken, M Chudzik, V Narayanan
Microelectronic Engineering 86(7-9), 1603--1608, Elsevier, 2009

High-$\kappa$/Metal Gate Science and Technology
S Guha, V Narayanan
Annual Review of Materials Research39, 181--202, Annual Reviews, 2009

Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
K Choi, Hi Jagannathan, C Choi, L Edge, T Ando, M Frank, P Jamison, M Wang, E Cartier, S Zafar, others
VLSI Technology, 2009 Symposium on, pp. 138--139


2008

Electrical and Materials Characterization of HfO2 and ZrO2 Thin Films for High-K Gate Applications Deposited by ALD in a 300 mm Reactor
Lisa F Edge, Paul Jamison, Hemanth Jagannathan, Barry P Linder, John Bruley, Matthew Copel, Jean Jordan-Sweet, Richard Murphy, Vijay Narayanan, Vamsi Paruchuri, others
Meeting Abstracts, pp. 643--643, 2008

Extendibility of NiPt silicide to the 22-nm node CMOS technology
Kazuya Ohuchi, Christian Lavoie, Conal E Murray, Chris P D'Emic, Isaac Lauer, Jack O Chu, Bin Yang, Paul Besser, Lynne M Gignac, John Bruley, others
Junction Technology, 2008. IWJT'08. Extended Abstracts-2008 8th International workshop on, pp. 150--153

Gate length scaling and high drive currents enabled for high performance SOI technology using high-$\kappa$/metal gate
K Henson, H Bu, MH Na, Y Liang, U Kwon, S Krishnan, J Schaeffer, R Jha, .., M Hargrove, D Guo, others
IEEE International Electron Devices Meeting, 2008, pp. 1--4

A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, D Jaeger, M Zaleski, HS Yang, others
VLSI Technology, 2008 Symposium on, pp. 88--89




2007



Process and Electrical Characteristics of MO-ALD HfO2 Films for High-k Gate Applications Grown in a Production Worthy 300 mm Deposition System
Robert D Clark, Cory S Wajda, Gert J Leusink, Lisa F Edge, Johnathan Faltermeier, Paul Jamison, Barry P Linder, Matthew Copel, Vijay Narayanan, Michael A Gribelyuk, others
ECS Transactions 11(3), 55--69, The Electrochemical Society, 2007

Dual layer SrTiO< sub> 3/HfO< sub> 2 gate dielectric for aggressively scaled band-edge nMOS devices
C Choi, E Cartier, YY Wang, V Narayanan, M Khare
Microelectronic engineering 84(9), 2217--2221, Elsevier, 2007

Examination of flatband and threshold voltage tuning of HfO 2/TiN field effect transistors by dielectric cap layers
S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, NA Bojarczuk, B Linder, B Doris
Applied Physics Letters 90(9), 092902--092902, AIP, 2007

Materials and process integration issues in metal gate/high-k stacks and their dependence on device performance
Alessandro Callegari, Katherina Babich, Sufi Zafar, Vijay Narayanan, Takashi Ando, Philip E Batson
ECS Transactions 11(4), 265--274, The Electrochemical Society, 2007

Recent advances and current challenges in the search for high mobility band-edge high-k/metal gate stacks
V Narayanan, VK Paruchuri, E Cartier, BP Linder, N Bojarczuk, S Guha, SL Brown, Y Wang, M Copel, TC Chen
Microelectronic engineering 84(9-10), 1853--1856, Elsevier, 2007

High-k/Metal Gates-from research to reality
V Narayanan
Physics of Semiconductor Devices, 2007, pp. 42--45

Band Edge High-$\kappa$/Metal Gate n-MOSFETs Using Ultra Thin Capping Layers
VK Paruchuri, V Narayanan, BP Linder, SL Brown, YH Kim, Y Wang, P Ronsheim, R Jammy, TC Chen
VLSI Technology, Systems and Applications, 2007, pp. 1--2

Examination of flatband and threshold voltage tuning of HfO/ TiN field effect transistors by dielectric cap layers
S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, NA Bojarczuk, B Linder, B Doris
Applied Physics Letters90, 092902, 2007

High-Performance High-k/Metal Gates for 45nm CMOS and Beyond with Gate-First Processing
M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, W Natzle, W Yan, others
2007 IEEE Symposium on VLSI Technology, pp. 194--195


Oxygen vacancies in high dielectric constant oxide-semiconductor films
S Guha, V Narayanan
Physical review letters 98(19), 196101, APS, 2007


2006

Charge Trapping, Negative Bias Temperature Instability (NBTI) and Breakdown related Reliability Issues in High k/Gate Dielectric Stacks
Sufi Zafar, Alexander Vayshenker, Alessando Callegari, Evgeni Gusev, Vijay Narayanan, Gilbert Singco
Meeting Abstracts, pp. 560--560, 2006

Dual Workfunction CMOS High-k-Metal Gates for High Performance Logic Technologies
Raj Jammy, Vijay Narayanan, Eduard Cartier
Meeting Abstracts, pp. 556--556, 2006

Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem
Supratik Guha, Vijay Narayanan, Vamsi Paruchuri, Barry Linder, Matthew Copel, Nestor Bojarczuk, Young-Hee Kim, Michael Chudzik, Yun Wang, Paul Ronsheim
ECS Transactions 3(2), 247--252, The Electrochemical Society, 2006

A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates
S Zafar, YH Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, A Callegari, M Chudzik
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on, pp. 23--25

Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack
E Cartier, BP Linder, V Narayanan, VK Paruchuri
Electron Devices Meeting, 2006. IEDM'06. International, pp. 1--4

Advanced high-$\kappa$ dielectric stacks with polySi and metal gates: recent progress and current challenges
Evgeni P Gusev, Vijay Narayanan, Martin M Frank
IBM journal of research and development 50(4/5), 387--410, IBM Corp., 2006

A comparative study of NBTI and PBTI in SiO2/HfO2 stacks with FUSI, TiN, gates
S Zafar, YH Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, A Callegari, M Chudzik
Pro. of VLSI Technology symp, 2006

Advanced High-k Dielectric Stacks with poly-Si and Metal Gates: Recent Progress and Current Challenges
E. P. Gusev, V. Narayanan and M. M. Frank
IBM Journal of Research and Development 50, 387, 2006

Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond
V Narayanan, VK Paruchuri, NA Bojarczuk, BP Linder, B Doris, YH Kim, S Zafar, J Stathis, S Brown, J Arnold, others
VLSI Technology, 2006, pp. 178--179

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks
V Narayanan, K Maitra, BP Linder, VK Paruchuri, EP Gusev, P Jamison, MM Frank, ML Steen, D La Tulipe, J Arnold, others
Electron Device Letters, IEEE 27(7), 591--594, IEEE, 2006

Poly-Si/AlN/HfSiO stack for ideal threshold voltage and mobility in sub-100 nm MOSFETs
KL Lee, MM Frank, V Paruchuri, E Cartier, B Linder, N Bojarczuk, X Wang, J Rubino, M Steen, P Kozlowski, others
VLSI Technology, 2006, pp. 160--161

Transistor scaling with novel materials
M Ieong, V Narayanan, D Singh, A Topol, V Chan, Z Ren
Materials Today 9(6), 26--31, Elsevier, 2006


2005

Potential imaging of Si/HfO 2/polycrystalline silicon gate stacks: Evidence for an oxide dipole
R Ludeke, V Narayanan, EP Gusev, E Cartier, SJ Chey
Applied Physics Letters 86(12), 122901--122901, AIP, 2005

HfO 2/metal stacks: determination of energy level diagram, work functions \& their dependence on metal deposition
S Zafar, V Narayanan, A Callegari, FR McFeely, P Jamison, E Gusev, C Cabral, R Jammy
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on, pp. 44--45

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility
MM Frank, VK Paruchuri, V Narayanan, N Bojarczuk, B Linder, S Zafar, EA Cartier, EP Gusev, PC Jamison, KL Lee, others
VLSI Technology, 2005.(VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on, pp. 97--98

Role of oxygen vacancies in V FB/V t stability of pFET metals on HfO 2
E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, VK Paruchuri, VS Basker, R Haight, D Lim, others
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on, pp. 230--231

Ultra-thin SOI replacement gate CMOS with ALD TaN/high-k gate stack
B Doris, DG Park, K Settlemyer, P Jamison, D Boyd, Y Li, J Hagan, T Staendert, J Mezzapelli, D Dobuzinsky, others
VLSI Technology, 2005, pp. 101--102

High performance FDSOI CMOS technology with metal gate and high-k
B Doris, YH Kim, BP Linder, M Steen, V Narayanan, D Boyd, J Rubino, L Chang, J Sleight, A Topol, others
VLSI Technology, 2005, pp. 214--215


2004

Reliability of MOS devices with tungsten gates
F Palumbo, S Lombardo, JH Stathis, V Narayanan, FR McFeely, JJ Yurkas
Microelectronic engineering 72(1), 45--49, Elsevier, 2004

Dual workfunction fully silicided metal gates
C Cabral, J Kedzierski, B Linder, S Zafar, V Narayanan, S Fang, A Steegen, P Kozlowski, R Carruthers, R Jammy
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, pp. 184--185

Interface engineering for enhanced electron mobilities in W/HfO2 gate stacks
A. Callegari, P. Jamison, E. Carrier, S. Zafar, E. Gusev, V. Narayanan, C. D'Emic, D. Lacey, F.M. Feely, R. Jammy
IEEE International Electron Devices Meeting, 2004. IEDM Technical Digest, pp. 825-828

The physical properties of cubic plasma-enhanced atomic layer deposition TaN films
H Kim, C Lavoie, M Copel, V Narayanan, D-G Park, SM Rossnagel
Journal of applied physics 95(10), 5848--5855, AIP Publishing, 2004

Charge trapping in aggressively scaled metal gate/high-k stacks
EP Gusev, V Narayanan, S Zafar, C Cabral Jr, E Carrier, N Bojarczuk, A Callegari, R Carruthers, M Chudzik, C D'Emic, others
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 729--732

Systematic study of pFET V< sub> t with Hf-based gate stacks with poly-Si and FUSI gates
E Cartier, V Narayanan, EP Gusev, P Jamison, B Linder, M Steen, KK Chan, M Frank, N Bojarczuk, M Copel, others
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, pp. 44--45

Advanced gate stacks with fully silicided (FUSI) gates and high-$\kappa$ dielectrics: enhanced performance at reduced gate leakage
EP Gusev, C Cabral Jr, BP Under, YH Kim, K Maitra, E Carrier, H Nayfeh, R Amos, G Biery, N Bojarczuk, others
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 79--82

Thermally robust dual-work function ALD-MN< sub> x MOSFETs using conventional CMOS process flow
D-G Park, ZJ Luo, N Edleman, W Zhu, P Nguyen, K Wong, C Cabral, P Jamison, BH Lee, A Chou, others
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on, pp. 186--187


2003

Growth and characterization of epitaxial Si/(LaxY1-x) 2O3/Si heterostructures
Narayanan, Vijay and Guha, Supratik and Bojarczuk, Nestor A and Ross, Frances M
Journal of applied physics93, 251--258, 2003

Interfacial Reactions of Metal Oxide Stack Dielectrics Studied with Medium Energy Ion Scattering
M Copel, MC Reuter, E Cartier, A Callegari, S Guha, EP Gousev, P Jamison, V Narayanan, D Neumayer
APS March Meeting Abstracts, pp. 6003, 2003

Growth and characterization of epitaxial Si/(La x Y 1-x) 2 O 3/Si heterostructures
Vijay Narayanan, Supratik Guha, Nestor A Bojarczuk, Frances M Ross
Journal of applied physics 93(1), 251--258, AIP, 2003

Growth and characterization of epitaxial Si/(La [sub x] Y [sub 1- x])[sub 2] O [sub 3]/Si heterostructures
V Narayanan, S Guha, NA Bojarczuk, FM Ross
Journal of Applied Physics 93(1), 251, 2003

Evaluation of CMOS gate metal materials using in situ characterization techniques
C CABRAL, C LAVOIE, AS OZCAN, RS AMOS, V NARAYANAN, EP GUSEV, JL JORDAN-SWEET, JME HARPER
Proceedings-Electrochemical Society, pp. 375--384, 2003

Epitaxial silicon and germanium on buried insulator heterostructures and devices
NA Bojarczuk, M Copel, S Guha, V Narayanan, EJ Preisler, FM Ross, H Shang
Applied physics letters 83(26), 5443--5445, AIP Publishing, 2003

‘Low Tinv (1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications
V Ku, R Amos, A Steegen, JC Cabral, V Narayanan, P Jamison, P Nguyen, Y Li, M Gribelyuk, Y Wang, others
Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, pp. 730

Device design considerations for ultra-thin SOI MOSFETs
B Doris, M Ieong, T Zhu, Y Zhang, M Steen, W Natzle, S Callegari, V Narayanan, J Cai, SH Ku, others
Electron Devices Meeting, 2003, pp. 27--3


2002


Stacking faults and twins in gallium phosphide layers grown on silicon
V Narayanan, S Mahajan, KJ Bachmann, V Woods, N Dietz
Philosophical Magazine A 82(4), 685--698, Taylor \& Francis, 2002


Characterization of silicate/Si (001) interfaces
M Copel, E Cartier, V Narayanan, MC Reuter, S Guha, N Bojarczuk
Applied physics letters 81(22), 4227--4229, AIP Publishing, 2002

Antiphase boundaries in GaP layers grown on (001) Si by chemical beam epitaxy
V Narayanan, S Mahajan, KJ Bachmann, V Woods, N Dietz
Acta materialia 50(6), 1275--1287, Elsevier, 2002

Interfacial oxide formation and oxygen diffusion in rare earth oxide--silicon epitaxial heterostructures
V Narayanan, S Guha, M Copel, NA Bojarczuk, PL Flaitz, M Gribelyuk
Applied physics letters81, 4183, 2002

Influence of AlN nucleation layer growth conditions on quality of GaN layers deposited on (0 0 0 1) sapphire
M Gonsalves, W Kim, V Narayanan, S Mahajan
Journal of crystal growth 240(3-4), 347--354, Elsevier, 2002

Gallium nitride epitaxy on (0001) sapphire
V Narayanan, K Lorenz, W Kim, S Mahajan
Philosophical Magazine A 82(5), 885--912, Taylor \& Francis, 2002

Impact of moisture on charge trapping and flatband voltage in Al2O3 gate dielectric films
S Zafar, A Callegari, V Narayanan, S Guha
Applied physics letters 81(14), 2608--2610, AIP, 2002


2001



2000


Orientation mediated self-assembled gallium phosphide islands grown on silicon
V Narayanan, S Mahajan, N Sukidi, KJ Bachmann, V Woods, N Dietz
Philosophical Magazine A 80(3), 555--572, Taylor \& Francis, 2000


1999

Initial stages of heteroepitaxy of GaP on selected silicon surfaces
N Sukidi, KJ Bachmann, V Narayanan, S Mahajan
Journal of the Electrochemical Society146, 1147, 1999

Origins of defects in self assembled GaP islands grown on Si (001) and Si (111)
V Narayanan, N Sukidi, KJ Bachmann, S Mahajan
Thin Solid Films 357(1), 53--56, Elsevier, 1999


1998

Growth of gallium phosphide layers by chemical beam epitaxy on oxide patterned (001) silicon substrates
V Narayanan, N Sukidi, Chimin Hu, N Dietz, KJ Bachmann, S Mahajan, S Shingubara
Materials Science and Engineering: B 54(3), 207--209, Elsevier, 1998


Year Unknown

The Interaction Challenges with Novel Materials in Developing High-Performance and Low-Leakage High-k/Metal Gate CMOS Transistors
Michael Chudzik, Siddarth Krishnan, Unoh Kwon, Mukesh Khare, Vijay Narayanan, Takashi Ando, Ed Cartier, Huiming Bu, Vamsi Paruchuri
High-k Gate Dielectrics for CMOS Technology, 531--555, Wiley Online Library, 0