Vijay Narayanan  Vijay Narayanan photo       

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Manager and Distinguished Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE   |  Materials Research Society (MRS)


2016


MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS
Alptekin, Emre and Kwon, Unoh and Lai, Wing L and Li, Zhengwen and Narayanan, Vijay and Ramachandran, Ravikumar and Vega, Reinaldo A
US Patent 20,160,035,841

Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure
Dubourdieu, Catherine A and Frank, Martin M and Narayanan, Vijay
US Patent 9,299,799

Method to improve reliability of high-K metal gate stacks
Ando, Takashi and Cartier, Eduard A and Linder, Barry P and Narayanan, Vijay
US Patent 9,299,802


Lowering parasitic capacitance of replacement metal gate processes
Leobandung, Effendi and Narayanan, Vijay
US Patent 9,257,289

High-k/metal gate transistor with L-shaped gate encapsulation layer
Mo, Renee T and Natzle, Wesley C and Narayanan, Vijay and Sleight, Jeffrey W
US Patent 9,263,276

Low threshold voltage CMOS device
Ando, Takashi and Choi, Changhwan and Choi, Kisik and Narayanan, Vijay
US Patent 9,263,344


2015

Multiple thickness gate dielectrics for replacement gate field effect transistors
Kwon, Unoh and Lai, Wing L and Narayanan, Vijay and Polvino, Sean M and Ramachandran, Ravikumar and Siddiqui, Shahab
US Patent 9,224,826

Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
Ando, Takashi and Cartier, Eduard A and Choi, Kisik and Lai, Wing L and Narayanan, Vijay and Ramachandran, Ravikumar
US Patent App. 14/707,822

Oxygen scavenging spacer for a gate electrode
Chudzik, Michael P and Nair, Deleep R and Narayanan, Vijay and Radens, Carl J and Shah, Jay M
US Patent 9,196,707

Annealing oxide gate dielectric layers for replacement metal gate field effect transistors
Kwon, Unoh and Lai, Wing L and Narayanan, Vijay and Ramachandran, Ravikumar and Siddiqui, Shahab
US Patent 9,177,868

Method to improve reliability of replacement gate device
Ando, Takashi and Cartier, Eduard A and Choi, Kisik and Narayanan, Vijay
US Patent 8,999,831

SEMICONDUCTOR CONTACT WITH DIFFUSION-CONTROLLED IN SITU INSULATOR FORMATION
Breil, Nicolas L and Narayanan, Vijay and Ozcan, Ahmet S and Schonenberg, Kathryn T
US Patent 20,150,270,168

Replacement metal gate structure for CMOS device
Ando, Takashi and Choi, Kisik and Narayanan, Vijay
US Patent 9,041,118

Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET
Ando, Takashi and Choi, Changhwan and Frank, Martin M and Kwon, Unoh and Narayanan, Vijay
US Patent 9,105,745


2014

Field effect transistor device having a hybrid metal gate stack
Cabral Jr, Cyril and Chang, Josephine B and Chudzik, Michael P and Frank, Martin M and Guillorn, Michael A and Lavoie, Christian and Narasimha, Shreesh and Narayanan, Vijay
US Patent 8,836,048

Structures and techniques for atomic layer deposition
Aoyama, Shintaro and Clark, Robert D and Consiglio, Steven P and Hopstaken, Marinus and Jagannathan, Hemanth and Jamison, Paul Charles and Leusink, Gert and Linder, Barry Paul and Narayanan, Vijay and Wajda, Cory and others
US Patent 8,722,548

Devices and methods to optimize materials and properties for replacement metal gate structures
Ando, Takashi and Lavoie, Christian and Narayanan, Vijay
US Patent 8,796,784

Multiple Vt field-effect transistor devices
Chang, Josephine B and Chang, Leland and Mo, Renee T and Narayanan, Vijay and Sleight, Jeffrey W
US Patent 8,878,298

FET device with stabilized threshold modifying material
Copel, Matthew W and Doris, Bruce B and Narayanan, Vijay and Wang, Yun-Yu
US Patent 8,735,243

Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
Jagannathan, Hemanth and Ando, Takashi and Narayanan, Vijay
US Patent 8,748,991

Changing effective work function using ion implantation during dual work function metal gate integration
Chudzik, Michael P and Frank, Martin M and Ho, Herbert L and Hurley, Mark J and Jha, Rashmi and Moumen, Naim and Narayanan, Vijay and Park, Dae-Gyu and Paruchuri, Vamsi K
US Patent 8,753,936

Reliable physical unclonable function for device authentication
John Bruley, Vijay Narayanan, Dirk Pfeiffer, Jean-Oliver Plouchart, Peilin Song
US Patent 8,741,713

Replacement gate structure for transistor with a high-K gate stack
Takashi Ando, Eduard A Cartier, Unoh Kwon, Vijay Narayanan
US Patent 8,716,118


2013

Self-limiting oxygen seal for high-K dielectric and design structure
Hook, Terence B and Narayanan, Vijay and Shah, Jay M and Sherony, Melanie J and Stein, Kenneth J and Wang, Helen H and Zhu, Chendong
US Patent 8,564,074

Epitaxial source/drain contacts self-aligned to gates for deposited FET channels
Josephine B Chang, Paul Chang, Vijay Narayanan, Jeffrey W Sleight
US Patent 8,513,099

High performance CMOS circuits, and methods for fabricating same
John C Arnold, Glenn A Biery, Alessandro C Callegari, Tze-Chiang Chen, Michael P Chudzik, Bruce B Doris, Michael A Gribelyuk, Young-Hee Kim, Barry P Linder, Vijay Narayanan, others
US Patent 8,383,483

Replacement gate devices with barrier metal for simultaneous processing
Takashi Ando, Michael P Chudzik, Siddarth A Krishnan, Unoh Kwon, Vijay Narayanan
US Patent 8,420,473

Method of forming switching device having a molybdenum oxynitride metal gate
Nestor A Bojarczuk, Michael P Chudzik, Matthew W Copel, Supratik Guha, Richard A Haight, Vijay Narayanan, Martin P O'boyle, Vamsi K Paruchuri
US Patent 8,518,766

Gate-last fabrication of quarter-gap MGHK FET
Takashi Ando, Kisik Choi, Vijay Narayanan, Tenko Yamashita, Junli Wang
US Patent 8,592,296


Scavanging metal stack for a high-k gate dielectric
Takashi Ando, Changhwan Choi, Martin M Frank, Vijay Narayanan
US Patent 8,367,496

Scaled equivalent oxide thickness for field effect transistor devices
Takashi Ando, Changhwan Choi, Unoh Kwon, Vijay Narayanan
US Patent 8,343,839


2012


Low Threshold Voltage And Inversion Oxide thickness Scaling For A High-K Metal Gate P-Type MOSFET
Takashi Ando, Changhwan Choi, Martin M Frank, Unoh Kwon, Vijay Narayanan
US Patent App. 13/630,235

Method of forming metal/high-$\kappa$ gate stacks with high mobility
Wanda Andreoni, Alessandro C Callegari, Eduard A Cartier, Alessandro Curioni, PD Christopher, Evgeni Gousev, Michael A Gribelyuk, Paul C Jamison, Rajarao Jammy, Dianne L Lacey, others
US Patent 8,153,514


Structure and method to obtain EOT scaled dielectric stacks
Takashi Ando, Changhwan Choi, Lisa F Edge, Hemanth Jagannathan, Paul C Jamison, Vijay Narayanan, Vamsi K Paruchuri, Sufi Zafar
US Patent 8,304,836

Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device
Takashi Ando, Eduard A Cartier, Changhwan Choi, Bruce B Doris, Elizabeth A Duch, Young-Hee Kim, Vijay Narayanan, James Pan, Vamsi K Paruchuri
US Patent 8,097,500


2011

Gate effective-workfunction modification for CMOS
Michael P Chudzik, Rashmi Jha, Siddarth A Krishnan, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi Paruchuri
US Patent 7,947,549

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices
Eduard A Cartier, Matthew W Copel, Bruce B Doris, Rajarao Jammy, Young-Hee Kim, Barry P Linder, Vijay Narayanan, Vamsi K Paruchuri, Keith Kwong Hon Wong
US Patent 7,999,323

Simple low power circuit structure with metal gate and high-k dielectric
Eduard Albert Cartier, Bruce B Doris, Barry Paul Linder, Vijay Narayanan, Vamsi Paruchuri
US Patent 7,880,243

Scavenging metal stack for a high-k gate dielectric
Takashi Ando, Changhwan Choi, Martin M Frank, Vijay Narayanan
US Patent 7,989,902


Ferroelectric Semiconductor Transistor Devices having gate modulated conductive layer
Catherine A Dubourdieu, David J Frank, Martin M Frank, Vijay Narayanan, Paul M Solomon, Thomas N Theis
US Patent App. 13/108,340



2010

Planar and non-planar CMOS devices with multiple tuned threshold voltages
Jagannathan, Hemanth and Narayanan, Vijay and Paruchuri, Vamsi K
US Patent 7,855,105

CMOS transistors with differential oxygen content high-K dielectrics
Bu, Huiming and Cartier, Eduard A and Doris, Bruce B and Kim, Young-Hee and Linder, Barry and Narayanan, Vijay and Paruchuri, Vamsi K and Steen, Michelle L
US Patent 7,696,036

Engineering multiple threshold voltages in an integrated circuit
Catherine Anne Dubourdieu, Martin Michael Frank, Vijay Narayanan
US Patent App. 12/899,691

Techniques for enabling multiple Vt devices using high-K metal gate stacks
Martin M Frank, Arvind Kumar, Vijay Narayanan, Vamsi K Paruchuri, Jeffrey Sleight
US Patent 7,718,496


Semiconductor device having dual metal gates and method of manufacture
Takashi Ando, Michael P Chudzik, Martin M Frank, William K Henson, Rashmi Jha, Siddarth A Krishnan, Unoh Kwon, Yue Liang, Vijay Narayanan, Ravikumar Ramachandran, others
US Patent 7,838,908


Metal gate high-K devices having a layer comprised of amorphous silicon
T C Chen, B B Doris, V Narayanan, V Paruchuri
US Patent 7,847,356

Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode
A C Callegari, T C Chen, M P Chudzik, B B Doris, Y H Kim, V Narayanan, V K Paruchuri, M L Steen, Y Zhang, others
US Patent 7,833,849

Method and apparatus for dynamic web service client application update
Y. Chen, R. Fang, L.L. Fong, D.C. Frank, L.H. Lam
US Patent 7,822,840

Formation of fully silicided metal gate using dual self-aligned silicide process
C Cabral Jr, C T Dziobkowski, S Fang, E Gousev, R Jammy, V Narayanan, V Paruchuri, G G Shahidi, M L Steen, C H Wann, others
US Patent 7,785,999

Disposable metallic or semiconductor gate spacer
S W Bedell, M Chudzik, W K Henson, N Moumen, V Narayanan, D K Sadana, K T Schonenberg, G Shahidi, others
US Patent 7,682,917

Method for composition control of a metal compound film
R D Allen, S L Brown, A C Callegari, M P Chudzik, V Narayanan, V K Paruchuri
US Patent 7,772,016


2009

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics
Nestor A Bojarczuk Jr, Cyril Cabral Jr, Eduard A Cartier, Matthew W Copel, Martin M Frank, Evgeni P Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K Paruchuri, others
US Patent 7,479,683

Removal of charged defects from metal oxide-gate stacks
Eduard A Cartier, Matthew W Copel, Supratik Guha, Richard A Haight, Fenton R McFeely, Vijay Narayanan
US Patent 7,488,656


2008

Metal gate CMOS with at least a single gate metal and dual gate dielectrics
Doris, Bruce B and Kim, Young-Hee and Linder, Barry P and Narayanan, Vijay and Paruchuri, Vamsi K
US Patent 7,432,567

CMOS silicide metal gate integration
Ricky S Amos, Diane C Boyd, Cyril Cabral Jr, Richard D Kaplan, Jakub T Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C Mocuta, Vijay Narayanan, others
US Patent 7,411,227

Semiconductor structure including mixed rare earth oxide formed on silicon
N A Bojarczuk Jr, D A Buchanan, S Guha, V Narayanan, L A Ragnarsson
US Patent 7,432,550

INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES
M P Chudzik, B B Doris, S Guha, R Jammy, V Narayanan, V K Paruchuri, Y Y Wang, K Hon, W Keith
EP Patent 1,974,372

METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-K GATE DIELECTRIC STACKS
S ZAFAR, A CALLEGARI, M CHUDZIK, V NARAYANAN, V PARUCHURI, B LINDER, D G PARK, R MO
WO Patent WO/2008/098,890


2007

GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER
Huiming Bu, Rick Carter, Michael P Chudzik, Troy L Graves, Michael A Gribelyuk, Rashmi Jha, Vijay Narayanan, Dae-Gyu Park, Vamsi K Paruchuri, Hongwen Yan, others
US Patent App. 11/958,595

HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS
Michael P Chudzik, Naim Moumen, Vijay Narayanan, Dae-Gyu Park, Vamsi K Paruchuri
US Patent App. 11/954,749

SCALABLE HIGH-K DIELECTRIC GATE STACK
Changhwan Choi, Takashi Ando, Kisik Choi, Vijay Narayanan
US Patent App. 11/928,391

NITROGEN-CONTAINING FIELD EFFECT TRANSISTOR GATE STACK CONTAINING A THRESHOLD VOLTAGE CONTROL LAYER FORMED VIA DEPOSITION OF A METAL OXIDE
N A Bojarczuk Jr, C Cabral Jr, E A Cartier, M M Frank, E P Gousev, S Guha, P C Jamison, R Jammy, V Narayanan, V K Paruchuri, others
EP Patent 1,825,521

SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS
N A Bojarczuk Jr, C Cabral Jr, E A Cartier, M W Copel, M M Frank, E P Gousev, S Guha, R Jammy, V Narayanan, V K Paruchuri, others
EP Patent 1,766,691


2006

Field effect transistor with etched-back gate dielectric
Saenger, Katherine L and Jammy, Rajarao and Narayanan, Vijay
US Patent 7,071,122

Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures
Cabral Jr, Cyril and Callegari, Alessandro C and Gribelyuk, Michael A and Jamison, Paul C and Lacey, Dianne L and McFeely, Fenton R and Narayanan, Vijay and Neumayer, Deborah A and Ranade, Pushkar and Zafar, Sufi and others
US Patent 6,982,230


2005

Method of forming lattice-matched structure on silicon and structure formed thereby
Nestor Alexander Bojarczuk Jr, Douglas Andrew Buchanan, Supratik Guha, Vijay Narayanan, Lars-Ake Ragnarsson
US Patent 6,852,575

Method for forming metal replacement gate of high performance
Cyril Cabral Jr, Paul C Jamison, Victor Ku, Ying Li, Vijay Narayanan, An L Steegen, Yun-Yu Wang, Kwong H Wong
US Patent 6,921,711

High performance CMOS circuits, and methods for fabricating the same
John C Arnold, Glenn A Biery, Alessandro C Callegari, Tze-Chiang Chen, Michael P Chudzik, Bruce B Doris, Michael A Gribelyuk, Young-Hee Kim, Barry P Linder, Vijay Narayanan, others
US Patent App. 11/323,578

CVD TANTALUM COMPOUNDS FOR FET GATE ELECTRODES
V NARAYANAN, F MCFEELY, K MILKOVE, J YURKAS, M COPEL, P JAMISON, R CARRUTHERS, C CABRAL JNR, E SIKORSKI, E DUCH, others
WO Patent WO/2005/047,561


2003

HIGH TEMPERATURE PROCESSING COMPATIBLE METAL GATE ELECTRODE FOR PFETS AND METHOD FOR FABRICATION
R AMOS, D BUCHANAN, C CABRAL Jr, A CALLEGARI, S GUHA, H KIM, F MCFEELY, V NARAYANAN, K RODBELL, J YURKAS
WO Patent WO/2003/046,998


2001

High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
Ricky Amos, Douglas Buchanan, Cyril Cabral, Alessandro Callegari, Supratik Guha, Hyungjun Kim, Fenton McFeely, Vijay Narayanan, Kenneth Rodbell, John Yurkas, others