Viresh Paruthi  Viresh Paruthi photo       

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STSM Formal Verification, Member Academy of Technology
Austin TX, USA
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2016

Calculating an immediate parent assertion statement for program verification
Paruthi, Viresh and Purandare, Mitra
US Patent 9,436,582
Abstract

Verifying forwarding paths in pipelines
Arunagiri, Anand B and Krautz, Udo and Kumar, Sujeet and Paruthi, Viresh
US Patent 9,459,878
Abstract

Formal verification of arbiters
Auerbach, Gadiel and Copty, Fady and Paruthi, Viresh
US Patent 9,280,496
Abstract

Providing a power optimized design for a device
Dhanwada, Nagashyamala R and Paruthi, Viresh
US Patent App. 14/987,160
Abstract


2014

Verifying data intensive state transition machines related application
Paruthi, Viresh and Sandon, Peter Anthony and Sawada, Jun
US Patent 8,756,543
Abstract

Optimizing a netlist circuit representation by leveraging binary decision diagrams to perform rewriting
Baumgartner, Jason and Janssen, Geert and Kanzelman, Robert and Paruthi, Viresh
US Patent 8,799,837
Abstract

Circuit verification using computational algebraic geometry
Janssen, Gradus Geert and Lastras-Montano, Luis and Lvov, Alexey Y and Paruthi, Viresh and Shadowen, Robert and Trager, Barry M and Winograd, Shmuel and El-Zein, Ali
US Patent 8,640,065
Abstract


2013

Formal verification of random priority-based arbiters using property strengthening and underapproximations
Auerbach, Gadiel and Copty, Fady and Levitt, David J and Paruthi, Viresh
US Patent 8,370,553
Abstract

Model checking in state transition machine verification
Paruthi, Viresh and Sandon, Peter Anthony and Sawada, Jun
US Patent 8,397,189
Abstract

Method and system for scalable reduction in registers with SAT-based resubstitution
Baumgartner, Jason R and Case, Michael L and Mony, Hari and Paruthi, Viresh
US Patent 8,473,882
Abstract


2012

Performing minimization of input count during structural netlist overapproximation
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 8,185,852
Abstract

Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 8,122,403
Abstract

Scalable reduction in registers with SAT-based resubstitution
Baumgartner, Jason R and Case, Michael L and Mony, Hari and Paruthi, Viresh
US Patent 8,201,115
Abstract

Method and structure for provably fair random number generator
Kailas, Krishnan Kunjunny and Monwai, Brian Chan and Paruthi, Viresh
US Patent 8,312,071
Abstract

Sequential encoding for relational analysis (SERA) of a software model
Baumgartner, Jason R and El-Zein, Ali S and Paruthi, Viresh and Zaraket, Fadi A
US Patent 8,141,048
Abstract


2011

Automated use of uninterpreted functions in sequential equivalence
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,996,803
Abstract

Method and system for sequential netlist reduction through trace-containment
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 8,015,523
Abstract

Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caring
Jacobi, Christian and Krautz, Udo and Paruthi, Viresh and Pflanz, Matthias and Weber, Kai O
US Patent 7,949,968
Abstract

Reduction of XOR/XNOR subexpressions in structural design representations
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,913,218
Abstract

Predicate selection in bit-level compositional transformations
Baumgartner, Jason R and Mony, Hari and Paruthi, Viresh and Zaraket, Fadi Z
US Patent 8,037,085
Abstract

Optimal simplification of constraint-based testbenches
Baumgartner, Jason and Kanzelman, Robert and Mony, Hari and Paruthi, Viresh
US Patent 7,913,208
Abstract

Method, system and application for sequential cofactor-based analysis of netlists
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 8,042,075
Abstract

Predicate-based compositional minimization in a verification environment
Baumgartner, Jason R and Mony, Hari and Paruthi, Viresh and Zaraket, Fadi A
US Patent 8,086,429
Abstract

Computer program product for design verification using sequential and combinational transformations
Baumgarter, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,996,800
Abstract

Enhanced verification through binary decision diagram-based target decomposition
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,921,394
Abstract

Incremental design reduction via iterative overapproximation and re-encoding strategies
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,930,672
Abstract

Incremental speculative merging
Baumgartner, Jason and Kanzelman, Robert and Mony, Hari and Paruthi, Viresh
US Patent 7,934,180
Abstract

Sequential equivalence checking for asynchronous verification
Baumgartner, Jason R and Ja, Yee and Mony, Hari and Paruthi, Viresh and Ramanandray, Barinjato
US Patent 7,882,473
Abstract

Enhancing formal design verification by reusing previous results
Paruthi, Viresh and Pouarz, Travis W and Williams, Mark A
US Patent 8,042,078
Abstract


2010

Building binary decision diagrams efficiently in a structural network representation of a digital circuit
Paruthi, Viresh and Jacobi, Christian and Janssen, Geert and Xu, Jiazhao and Weber, Kai Oliver
US Patent 7,836,413
Abstract

System for building binary decision diagrams efficiently in a structural network representation of a digital circuit
Paruthi, Viresh and Jacobi, Christian and Janssen, Geert and Xu, Jiazhao and Weber, Kai Oliver
US Patent 7,853,917
Abstract

System for verification of digital designs using case-splitting via constrained internal signals
Baumgartner, Jason Raymond and Jacobi, Christian and Paruthi, Viresh and Weber, Kai Oliver
US Patent 7,752,583
Abstract

Method and system for performing ternary verification
Baumgartner, Jason R and Mony, Hari and Paruthi, Viresh and Sustik, Matyas A
US Patent 7,734,452
Abstract

Bounded starvation checking of an arbiter using formal verification
Kailas, Krishnan Kunjunny and Monwai, Brian Chan and Paruthi, Viresh
US Patent 7,752,369
Abstract

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,743,353
Abstract

Method and system for performing heuristic constraint simplification
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,793,242
Abstract

Computer program product for extending incremental verification of circuit design to encompass verification restraints
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,779,378
Abstract

Formally deriving a minimal clock-gating scheme
Barowski, Harry and Butts, J Adam and Gemmeke, Tobias and Maeding, Nicolas and Paruthi, Viresh
US Patent 7,849,428
Abstract

Conjunctive BDD building and variable quantification using case-splitting
Baumgartner, Jason R and Jacobi, Christian and Paruthi, Viresh and Xu, Jiazhao
US Patent 7,739,635
Abstract

Parametric reduction of sequential design
Baumgartner, Jason Raymond and Janssen, Geert and Mony, Hari and Paruthi, Viresh
US Patent 7,689,943
Abstract


2009

Generating constraint preserving testcases in the presence of dead-end constraints
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,600,209
Abstract

Method and system for performing target enlargement in the presence of constraints
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,552,407
Abstract

Method and System for Automated Use of Uninterpreted Functions in Sequential Equivalence Checking
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent App. 12/362,513
Abstract

Extending incremental verification of circuit design to encompass verification restraints
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,509,605
Abstract

System for verification using reachability overapproximation
Baumgartner, Jason Raymond and Mony, Hari and Paruthi, Viresh and Xu, Jiazhao
US Patent 7,475,370
Abstract


2008

Computer program product for verification of digital designs using case-splitting via constrained internal signals
Baumgartner, Jason Raymond and Jacobi, Christian and Paruthi, Viresh and Weber, Kai Oliver
US Patent 7,458,048
Abstract

Trace equivalence identification through structural isomorphism detection with on the fly logic writing
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,398,488
Abstract

Enhanced structural redundancy detection
Baumgartner, Jason R and Mony, Hari and Paruthi, Viresh and Zaraket, Fadi Z
US Patent 7,360,181
Abstract

Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework
Baumgartner, Jason Raymond and Jacobi, Christian and Paruthi, Viresh and Weber, Kai
US Patent 7,340,704
Abstract

Method and system for enhanced verification through structural target decomposition
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,350,169
Abstract

Performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent App. 12/130,047
Abstract

Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals
Baumgartner, Jason Raymond and Jacobi, Christian and Paruthi, Viresh and Weber, Kai Oliver
US Patent 7,367,001
Abstract

Method and system for reversing the effects of sequential reparameterization on traces
Baumgartner, Jason Raymond and Janssen, Geert and Mony, Hari and Paruthi, Viresh
US Patent 7,350,166
Abstract

Method for incremental design reduction via iterative overapproximation and re-encoding strategies
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,370,292
Abstract

Method and system for reduction of XOR/XNOR subexpressions in structural design representations
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,340,694
Abstract

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables
Baumgartner, Jason Raymond and Janssen, Geert and Mony, Hari and Paruthi, Viresh
US Patent 7,350,179
Abstract

Method and system for performing minimization of input count during structural netlist overapproximation
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,380,222
Abstract

Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit
Paruthi, Viresh and Jacobi, Christian and Janssen, Geert and Xu, Jiazhao and Weber, Kai Oliver
US Patent 7,340,473
Abstract

Method for heuristic preservation of critical inputs during sequential reparameterization
Baumgartner, Jason Raymond and Janssen, Geert and Mony, Hari and Paruthi, Viresh
US Patent 7,370,298
Abstract

Using constraints in design verification
Baumgartner, Jason Raymond and Mony, Hari and Paruthi, Viresh and Xu, Jiazhao
US Patent 7,421,669
Abstract

Method for predicate-based compositional minimization in a verification environment
Baumgartner, Jason R and Mony, Hari and Paruthi, Viresh and Zaraket, Fadi A
US Patent 7,437,690
Abstract

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,356,792
Abstract

Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver
Baumgartner, Jason R and Kanzelman, Robert L and Mony, Hari and Paruthi, Viresh
US Patent 7,448,005
Abstract

Design verification using sequential and combinational transformations
Baumgarter, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,360,185
Abstract

Method for verification using reachability overapproximation
Baumgartner, Jason Raymond and Mony, Hari and Paruthi, Viresh and Xu, Jiazhao
US Patent 7,322,017
Abstract


2007


Method for retiming in the presence of verification constraints
Baumgartner, Jason Raymond and Mony, Hari and Paruthi, Viresh and Xu, Jiazhao
US Patent 7,203,915
Abstract

Method and system for performing functional verification of logic circuits
Weber, Kai and Jacobi, Christian and Gulden, Nico and Paruthi, Viresh and Keuerleber, Klaus
US Patent 7,302,656
Abstract

System and method for engine-controlled case splitting within multiple-engine based verification framework
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,266,795
Abstract

Method and system for optimized handling of constraints during symbolic simulation
Baumgartner, Jason Raymond and Jacobi, Christian and Paruthi, Viresh and Weber, Kai Oliver
US Patent 7,290,229
Abstract

Exploiting suspected redundancy for enhanced design verification
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,260,799
Abstract

Method for preserving constraints during sequential reparameterization
Baumgartner, Jason Raymond and Janssen, Geert and Mony, Hari and Paruthi, Viresh
US Patent 7,299,432
Abstract


2006

Method and system for predicate selection in bit-level compositional transformations
Baumgartner, Jason and Mony, Hari and Paruthi, Viresh and Zaraket, Fadi
US Patent App. 11/333,606
Abstract

Integrated design verification and design simplification system
Baumgartner, Jason Raymond and Mony, Hari and Paruthi, Viresh
US Patent 6,983,435
Abstract

Incremental, assertion-based design verification
Baumgartner, Jason Raymond and Kanzelman, Robert Lowell and Mony, Hari and Paruthi, Viresh
US Patent 7,093,218
Abstract

Use of time step information in a design verification system
Baumgartner, Jason Raymond and Mony, Hari and Paruthi, Viresh and Williams, Mark Allen
US Patent 6,993,734
Abstract

Method and System for Performing Functional Formal Verification of Logic Circuits
Jacobi, Christian and Paruthi, Viresh and Pflanz, Matthias and Weber, Kai
US Patent App. 11/467,651
Abstract


2004

Framework for multiple-engine based verification tools for integrated circuits
Baumgartner, Jason Raymond and Janssen, Geert and Kuehlmann, Andreas and Paruthi, Viresh and Trevillyan, Louise Helen
US Patent 6,698,003
Abstract


2002

Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis
Ganai, Malay Kumar and Janssen, Geert and Krohm, Florian Karl and Kuehlmann, Andreas and Paruthi, Viresh
US Patent 6,473,884
Abstract