Alessandro Cevrero  Alessandro Cevrero photo       

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Zurich Research Laboratory, Zurich, Switzerland



10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver
P.A. Francese, T. Toifl, M. Braendli, C. Menolfi, M. Kossel, T. Morf, L. Kull, T. Meyer Andersen, H. Yueksel, A. Cevrero
IEEE International Solid-State Circuits Conference (ISSCC) , pp. 1-3, 2015


A parallelized layered QC-LDPC decoder for IEEE 802.11 ad
A. Balatsoukas-Stimming, N. Preyss, A. Cevrero, A. Burg, C. Roth
IEEE 11th International New Circuits and Systems Conference (NEWCAS), pp. 1-4, 2013


Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders
C. Roth, A. Cevrero, C. Studer, Y. Leblebici, A. Burg
IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1772-1775, 2011

Power-gated mos current mode logic (pg-mcml): A power aware dpa-resistant standard cell library
A. Cevrero, F. Regazzoni, M. Schwander, S. Badel, P. Ienne, Y. Leblebici
48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1014-1019, 2011


A 5.35 mm 2 10GBASE-T Ethernet LDPC decoder chip in 90 nm CMOS
A. Cevrero, Y. Leblebici, P. Ienne, A. Burg
IEEE Asian Solid State Circuits Conference (A-SSCC), pp. 1-4, 2010

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
F. Sun, A. Cevrero, P. Athanasopoulos, Y. Leblebici
18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), pp. 149-154, 2010


Field programmable compressor trees: Acceleration of multi-input addition on FPGAs
A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A.K. Verma, H.S.A. Niaki, C. Nicopoulos, F.K. Gurkaynak, P. Brisk, Y. Leblebici, P. Ienne
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 2(2), 13, 2009

A flexible DSP block to enhance FPGA arithmetic performance
H. Parandeh-Afshar, A. Cevrero, P. Athanasopoulos, P. Brisk, Y. Leblebici, P. Ienne
IEEE International Conference on Field-Programmable Technology, pp. 70-77, 2009

3D configuration caching for 2D FPGAs
A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, P. Brisk, Y. Lebebici, P. Ienne, M. Skerlj
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, pp. 286, 2009

A design flow and evaluation framework for DPA-resistant instruction set extensions
F. Regazzoni, A. Cevrero, F.-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, P. Ienne
Cryptographic Hardware and Embedded Systems (CHES 2009), pp. 205-219, Springer