Heiner Giefers  Heiner Giefers photo       

contact information

Research Staff Member
Zurich Research Laboratory, Zurich, Switzerland
  +41dash44dash724dash84dash80

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Professional Associations

Professional Associations:  IEEE, Senior Member


2017

A hardware compilation framework for text analytics queries
Polig, Raphael and Atasu, Kubilay and Giefers, Heiner and Hagleitner, Christoph and Chiticariu, Laura and Reiss, Frederick and Zhu, Huaiyu and Hofstee, Peter
Journal of Parallel and Distributed Computing, Elsevier, 2017


2016

NanoStreams: Codesigned Microservers for Edge Analytics in Real Time
G. Georgakoudis, C. Gillan, A. Hassan, U. Minhas, G. Tzenakis, I. Spence, H. Vandierendonck, R. Woods, D.S. Nikolopoulos, M. Shyamsundar, P. Barber, M. Russell, A. Bilas, S. Kaloutsakis, H. Giefers, P. Staar, C. Bekas, N. Horlock, R. Faloon, C. Pattison
2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XVI) , pp. 8, IEEE

Energy-Efficient Stochastic Matrix Function Estimator for Graph Analytics on FPGA
Heiner Giefers, Peter Staar, Raphael Polig
Field Programmable Logic and Applications, 2016. FPL 2016. International Conference on, IEEE


Stochastic Matrix-Function Estimators: Scalable Big-Data Kernels with High Performance
Peter W. J. Staar, Panagiotis K. Barkoutsos, Roxana Istrate, A. Cristiano I. Malossi, Ivano Tavernelli, Nikolaj Moll, Heiner Giefers, Christoph Hagleitner, Costas Bekas, Alessandro Curioni
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp. 812-821
Abstract   Best Paper Award Winner

Analyzing the Energy-Efficiency of Sparse Matrix Multiplication on Heterogeneous Systems: A Comparative Study of GPU, Xeon Phi and FPGA
Heiner Giefers, Peter Staar, Costas Bekas, Christoph Hagleitner
Int. Symp. on Performance Analysis of Systems and Software (ISPASS), IEEE, 2016


2015

A fast, hybrid, power-efficient high-precision solver for large linear systems based on low-precision hardware
Christoph M. Angerer, Raphael Polig, Djordje Zegarac, Heiner Giefers, Christoph Hagleitner, Costas Bekas, Alessandro Curioni
Sustainable Computing: Informatics and Systems, Elsevier, 2015

Enabling Energy-Efficient Exascale Computing: Acceleration of HPC Kernels with Reconfigurable Hardware
Heiner Giefers
Platform for Advanced Scientific Computing Conference (PASC), 2015

Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT
Heiner Giefers, Raphael Polig, Christoph Hagleitner
Journal of Signal Processing Systems, 1--17, Springer US, 2015

A soft-core processor array for relational operators
Raphael Polig, Heiner Giefers, Walter Stechele
Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on, pp. 17--24

Accelerating arithmetic kernels with coherent attached FPGA coprocessors
Heiner Giefers, Raphael Polig, Christoph Hagleitner
Proceedings of the 2015 Design, Automation \& Test in Europe Conference \& Exhibition, pp. 1072--1077


2014

Accelerating finite difference time domain simulations with reconfigurable dataflow computers
Heiner Giefers, Christian Plessl, Jens Forstner
ACM SIGARCH Computer Architecture News 41(5), ACM, 2014

Compiling text analytics queries to FPGAs
Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu
24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014, pp. 1--6

Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system
Heiner Giefers, Raphael Polig, Christoph Hagleitner
Application-specific Systems, Architectures and Processors (ASAP), 2014 IEEE 25th International Conference on, pp. 92--99

An FPGA-based Reconfigurable Mesh Many-Core
Heiner Giefers, Marco Platzner
IEEE Transactions on Computers 63(12), IEEE, 2014


2013

Accelerating finite difference time domain simulations with reconfigurable dataflow computers
Heiner Giefers, Christian Plessl, Jens Forstner
Proceedings of 4th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, pp. 33--38, 2013


2012

Design and Programming of Reconfigurable Mesh Based Many-cores
Heiner Giefers
2012 - books.google.com, Logos Verlag Berlin GmbH


2010


A triple hybrid interconnect for many-cores: Reconfigurable mesh, NoC and Barrier
Heiner Giefers, Marco Platzner
Field Programmable Logic and Applications (FPL), 2010 International Conference on, pp. 223--228


2009

Program-driven fine-grained power management for the reconfigurable mesh
Heiner Giefers, Marco Platzner
Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, pp. 119--125

Towards Models for Many-Cores: The Case for the Reconfigurable Mesh
Heiner Giefers, Marco Platzner
Architecture of Computing Systems (ARCS), 2009 22nd International Conference on, pp. 1--10

ARMLang: a language and compiler for programming reconfigurable mesh many-cores
Heiner Giefers, Marco Platzner
Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on, pp. 1--8


2008

Reconfigurable many-cores with lean interconnect
Heiner Giefers
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on, pp. 707--708

Realizing reconfigurable mesh algorithms on softcore arrays
Heiner Giefers, Marco Platzner
Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on, pp. 41--48


2007

A many-core implementation based on the reconfigurable mesh model
Heiner Giefers, Marco Platzner
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on, pp. 41--46


2006

Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture
Heiner Giefers, Achim Rettberg
Proceedings of the 19th annual symposium on Integrated circuits and systems design, pp. 113--118, 2006