Raphael Polig  Raphael Polig photo       

contact information

Post-Doc Researcher
Zurich Research Laboratory, Zurich, Switzerland
  +41dash44dash724dash84dash46

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Professional Associations

Professional Associations:  IEEE


2017

Accelerated analysis of Boolean gene regulatory networks
Purandare, Mitra and Polig, Raphael and Hagleitner, Christoph
Field Programmable Logic and Applications (FPL), 2017 27th International Conference on, pp. 1--6
Abstract

A hardware compilation framework for text analytics queries
Polig, Raphael and Atasu, Kubilay and Giefers, Heiner and Hagleitner, Christoph and Chiticariu, Laura and Reiss, Frederick and Zhu, Huaiyu and Hofstee, Peter
Journal of Parallel and Distributed Computing, Elsevier, 2017

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs
Mukherjee, Rajdeep and Purandare, Mitra and Polig, Raphael and Kroening, Daniel
Proceedings of the 54th Annual Design Automation Conference 2017, pp. 35


2016

Energy-efficient stochastic matrix function estimator for graph analytics on FPGA
Heiner Giefers, Peter Staar, Raphael Polig
26th International Conference on Field Programmable Logic and Applications (FPL), 2016

Annotation-based finite-state transducers on reconfigurable devices
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama
Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, pp. 1--9


2015

Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT
Heiner Giefers, Raphael Polig, Christoph Hagleitner
Journal of Signal Processing Systems, 1--17, Springer US, 2015

A Fast, Hybrid, Power-Efficient High-Precision Solver for Large Linear Systems Based on Low-Precision Hardware
CM Angerer, R Polig, D Zegarac, H Giefers, C Hagleitner, C Bekas, A Curioni
Sustainable Computing: Informatics and Systems, Elsevier, 2015

A soft-core processor array for relational operators
Raphael Polig, Heiner Giefers, Walter Stechele
Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on, pp. 17--24

Accelerating arithmetic kernels with coherent attached FPGA coprocessors
Heiner Giefers, Raphael Polig, Christoph Hagleitner
Proceedings of the 2015 Design, Automation \& Test in Europe Conference \& Exhibition, pp. 1072--1077


2014

Compiling Text Analytics Queries to FPGAs
Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu
The 24th International Conference on Field Programmable Logic and Applications, pp. 1-6, 2014

Hardware-accelerated text analytics
R. Polig, K. Atasu, C. Hagleitner, L. Chiticariu, H. Zhu, F. Reiss, H. P. Hofstee
Hot Chips: A Symposium on High Performance Chips, 2014

Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system
Heiner Giefers, Raphael Polig, Christoph Hagleitner
Application-specific Systems, Architectures and Processors (ASAP), 2014 IEEE 25th International Conference on, pp. 92--99

Giving text analytics a boost
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H Peter Hofstee, Frederick R Reiss, Huaiyu Zhu, Eva Sitaridi
IEEE Micro 34(4), 6--14, IEEE, 2014


2013

Hardware-Accelerated Regular Expression Matching for High-Throughput Text Analytics
Kubilay Atasu, Raphael Polig, Christoph Hagleitner and Frederick. R. Reiss
23rd International Conference on Field Programmable Logic and Applications, pp. 1--7, IEEE, 2013

Token-based Dictionary Pattern Matching for Text Analytics
Raphael Polig, Kubilay Atasu, and Christoph Hagleitner
23rd International Conference on Field Programmable Logic and Applications, pp. 1--6, IEEE, 2013

Exploring The Design Space of Programmable Regular Expression Matching Accelerators
Kubilay Atasu, Raphael Polig, Jonathan Rohrer, and Christoph Hagleitner
Journal of Systems Architecture 59(10), 1184-1196, Elsevier, 2013
Abstract

A high-speed and large-scale dictionary matching engine for Information Extraction systems
Kanak Agarwal, Raphael Polig
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on, pp. 59--66