Charles Lefurgy  Charles Lefurgy photo       

contact information

Research Staff Member, Computing as a Service Technologies
Austin Research Laboratory, Austin, TX, USA

links

Professional Associations

Professional Associations:  ACM  |  IEEE  |  IEEE Computer Society


New publications

  • Yazhou Zu, Charles Lefurgy, Jingwen Leng, Matthew Halpern, Michael Floyd, and Vijay Janapa Reddi, "Adaptive guardband scheduling to improve system-level efficiency of the POWER7+", Proceedings of the 48th International Symposium on Microarchitecture, pp. 308-321, 2015.
    Paper: PDF
  • Arun Joseph, Anand Haridass, Charles Lefurgy, Sreekanth Pai, Spandana Rachamalla, and Francesco Campisano, "FreqLeak: A frequency step based method for efficient leakage power characterization in a system", 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 195-200, 2015.
  • Tobias Webel, Preetham Lobo, Ramon Bertran, Gerard Salem, Malcolm Allen-Ware, Richard Rizzolo, Sean Carey, Thomas Strach, Alper Buyuktosunoglu, Charles Lefurgy, Pradip Bose, Ricardo Nigaglioni, Timothy Slegel, Michael Floyd, and Brian Curran, "Robust power management in the IBM z13", IBM J. Res. & Dev., Vol. 59, No. 4/5, July/September 2015.
  • Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, and Vidushi Goyal, "FirmLeak: A framework for efficient and accurate runtime estimation of leakage power by firmware", 28th International Conference on VLSI Design (VLSID), 2015.
    Paper: PDF
    Poster: PDF

Categorized by type

Book chapters

  1. P. Bohrer, E. N. Elnozahy, T. Keller, M. Kistler, C. Lefurgy, C. McDowell, and R. Rajamony, "The Case for Power Management in Web Servers", published in Power Aware Computing, editors R. Melhem and R. Graybill, Kluwer Academic/Plenum Publishers, 2002.
    Chapter: PDF
    Order the book from Kluwer Academic/Plenum Publishers

Refereed journal articles

  1. Tobias Webel, Preetham Lobo, Ramon Bertran, Gerard Salem, Malcolm Allen-Ware, Richard Rizzolo, Sean Carey, Thomas Strach, Alper Buyuktosunoglu, Charles Lefurgy, Pradip Bose, Ricardo Nigaglioni, Timothy Slegel, Michael Floyd, and Brian Curran, "Robust power management in the IBM z13", IBM J. Res. & Dev., Vol. 59, No. 4/5, July/September 2015.
  2. Shinobu Miwa and Charles Lefurgy, "Evaluation of Core Hopping on POWER7", ACM SIGMETRICS Performance Evaluation Review, Vol. 42, Issue 3, pp. 55-60, 2014.
  3. Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, John Carter, and Robert Berry Jr., "Active Guardband Management in POWER7+ to Save Energy and Maintain Reliability", Micro, IEEE, Vol. 33, No. 4, pp. 35-45, Aug.-Sept., 2013.
    Paper: PDF
  4. Xiaorui Wang, Ming Chen, Charles Lefurgy, and Tom Keller, "SHIP: A Scalable Hierarchical Power Control Architecture for Large-Scale Data Centers ", IEEE Trans. on Parallel and Distributed Systems, 23(1): 168-176, January 2012. (Spotlight paper of the issue)
    Paper: PDF
    Supplementary Paper: PDF
  5. Michael Floyd, Bishop Brock, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, Jose A. Tierno, Pradip Bose, and Alper Buyuktosunoglu, "Introducing the Adaptive Energy Management Features of the POWER7 Chip ", IEEE Micro, vol. 31, no. 2, March/April, 2011.
    Paper: PDF
  6. Charles Lefurgy, Xiaorui Wang, and Malcolm Ware, "Power capping: a prelude to power shifting", Cluster Computing, Springer Netherlands, November 2007.
    Paper: PDF
    On Springer website
  7. Charles Lefurgy, Karthick Rajamani, Freeman Rawson, Wes Felter, Michael Kistler, Tom W. Keller, "Energy Management for Commercial Servers", IEEE Computer, pp. 39-48, December, 2003.
    Paper: PDF
  8. W.M. Felter, T.W. Keller, M.D. Kistler, C. Lefurgy, K. Rajamani, R. Rajamony, F.L. Rawson, B.A. Smith, and E. van Hensbergen, "On the performance and use of dense servers", IBM Journal of R & D, vol. 47, no. 5/6, pp. 671-688, Sept.-Nov., 2003.
    Paper: PDF

Refereed conference papers

  1. Yazhou Zu, Charles Lefurgy, Jingwen Leng, Matthew Halpern, Michael Floyd, and Vijay Janapa Reddi, "Adaptive guardband scheduling to improve system-level efficiency of the POWER7+", Proceedings of the 48th International Symposium on Microarchitecture, pp. 308-321, 2015.
    Paper: PDF
  2. Arun Joseph, Anand Haridass, Charles Lefurgy, Sreekanth Pai, Spandana Rachamalla, and Francesco Campisano, "FreqLeak: A frequency step based method for efficient leakage power characterization in a system", 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 195-200, 2015.
  3. Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, and Vidushi Goyal, "FirmLeak: A framework for efficient and accurate runtime estimation of leakage power by firmware", 28th International Conference on VLSI Design (VLSID), 2015.
    Paper: PDF
    Poster: PDF
  4. Subhasish Mitra, Pradip Bose, Eddie Cheng, Chen-Yong Cher, Hyeonwoo Cho, Rajan Joshi, Young Moon Kim, Charles Lefurgy, Yuhua Li, Kenneth Rodbell, Kevin Skadron, James Stathis, and Lukasz Szafaryn, "The resilience wall: Cross-layer solution strategies", Proceedings of Technical Program 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014.
  5. Wei Huang, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael Floyd, Karthick Rajamani, Malcolm Allen-Ware, and Bishop Brock, "Accurate Fine-Grained Processor Power Proxies", Proceedings of the 45th Annual International Symposium on Microarchitecture, December 2012. (Acceptance rate: 40/228 = 17.5%)
    Paper: PDF
    Slides: PDF
    Poster: PDF
    Summary slide: PDF
  6. Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, and John Carter, "Active Management of Timing Guardband to Save Energy in POWER7", Proceedings of the 44th Annual International Symposium on Microarchitecture, December 2011. MICRO-44 Best Paper Award. IBM Pat Goldberg Memorial Best Paper Award for 2011. (Acceptance rate: 44/209 = 21%)
    Paper: PDF
    Slides: PDF
    Video: WMV
  7. Wei Huang, Malcolm Allen-Ware, John B. Carter, Elmootazbellah Elnozahy, Hendrik Hamann, Tom Keller, Charles Lefurgy, Jian Li, Karthick Rajamani, and Juan Rubio, "TAPO: Thermal-Aware Power Optimization Techniques for Servers and Data Centers", International Green Computing Conference (IGCC'11), 2011. (Acceptance rate: 26/85 = 31%)
    Best paper award
    Paper: PDF
    Slides: PDF
  8. Xing Fu, Xiaorui Wang, and Charles Lefurgy, "How Much Power Oversubscription is Safe and Allowed in Data Centers?", The 8th International Conference on Autonomic Computing (ICAC 2011), Karlsruhe, Germany, June 2011. (Acceptance rate: 20/89 = 22%)
    Paper: PDF
    Slides: PDF
  9. Jian Li, Lixin Zhang, Charles Lefurgy, Wei Huang, Wolfgang Denzel, Richard Treumann, and Kun Wang, "Power Shifting in Thrifty Interconnection Network ", Proceedings of the 17th International Symposium on High-Performance Computer Architecture (HPCA), 2011. (Acceptance rate: 42/227 ˜ 18.5%)
    Paper: PDF
    Slides: PDF
  10. Xiaorui Wang, Ming Chen, Charles Lefurgy, and Tom W. Keller, "SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers", The Eighteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2009. (Acceptance rate: 35/188 = 18%)
    Paper: PDF
    Slides: PDF
  11. Anshul Gandhi, Mor Harchol-Balter, Rajarshi Das, and Charles Lefurgy, "Optimal Power Allocation in Server Farms", Proceedings of ACM SIGMETRICS 2009 Conference on Measurement and Modeling of Computer Systems. Seattle, WA, June 2009. (Acceptance rate: 27/180 = 15%)
    Paper: PDF
    Tech report: PDF (additional details)
    Slides: PPT
  12. Rajarshi Das, Jeffrey O. Kephart, Charles Lefurgy, Gerald Tesauro, David W. Levine, and Hoi Chan, "Autonomic Multi-Agent Management of Power and Performance in Data Centers", The 7th International Conference on Autonomous Agents and Multiagent Systems (AAMAS), 2008.
    Paper: PDF
  13. Gerald Tesauro, Rajarshi Das, Hoi Chan, Jeffrey Kephart, David Levine, Freeman Rawson, and Charles Lefurgy, "Managing Power Consumption and Performance of Computing Systems Using Reinforcement Learning", Proceedings of the Neural Information Processing Systems Conference (NIPS), 2007.
    Paper: PDF
    Slide: PDF
  14. Charles Lefurgy, Xiaorui Wang, and Malcolm Ware, "Server-level Power Control ", 4th IEEE Conference on Autonomic Computing (ICAC'07), 2007. (Acceptance rate: 16%)
    Paper: PDF
    Slides: PDF
  15. Jeffrey O. Kephart, Hoi Chan, Rajarshi Das, David W. Levine, Gerald Tesauro, Freeman Rawson, and Charles Lefurgy , "Coordinating multiple autonomic managers to achieve specified power-performance tradeoffs", 4th IEEE Conference on Autonomic Computing (ICAC'07), 2007.
    Paper: PDF
    Slides: PDF
  16. Hai Huang, Charles Lefurgy, Tom Keller, and Kang G. Shin, "Improving Energy Efficiency by Making DRAM Less Randomly Accessed", in Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED), August, 2005.
    Paper: PDF
    Paper: PS
    Slides: PowerPoint
  17. Juan Rubio, Charles Lefurgy, and Lizy K. John, "Improving Server Performance on Transaction Processing Workloads by Enhanced Data Placement", Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'04), October, 2004, pp. 84-91.
    Paper: PDF
    Slides: PowerPoint
  18. Karthick Rajamani and Charles Lefurgy, "On Evaluating Request-Distribution Schemes for Saving Energy in Server Clusters", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'03), March 2003.
    Paper: PDF
    Paper: PS
    Slides: PDF
  19. Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen, Ram Rajamony, and Raj Rajkumar, "Critical Power Slope: Understanding the Runtime Effects of Frequency Scaling", Proceedings of the 16th Annual ACM International Conference on Supercomputing (ICS'02), June 2002.
    Awarded Best Student Presentation (Akihiko Miyoshi).
    Paper: PDF
    Slides: Powerpoint
  20. Charles Lefurgy, Eva Piccininni, and Trevor Mudge, "Reducing Code Size with Run-time Decompression", Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA), January 2000.
    Paper: PDF
    Paper: PS
    Slides: PDF
    Slides: PS
  21. Charles Lefurgy, Eva Piccininni, and Trevor Mudge, "Analysis of a High Performance Code Compression Method", Proceedings of the 32th Annual International Symposium on Microarchitecture, pp. 93-102, November 1999.
    Paper: PDF
    Paper: PS
    Slides: PDF
    Slides: PS
  22. Charles Lefurgy and Trevor Mudge,"Fast Software-managed Code Decompression", Proceedings of CASES'99 (Computer and Architecture Support for Embedded Systems), pp. 139-143, October 1999.
    Presented at 10th Annual IPoCSE Review, University of Michigan
    Paper: PDF
    Paper: PS
    Slides: PDF
    Slides: PS
  23. Charles Lefurgy, Peter Bird, I-Cheng Chen, and Trevor Mudge, "Improving Code Density Using Compression Techniques", Proceedings of the 30th Annual International Symposium on Microarchitecture, pp. 194-203, December 1997.
    ps.Z (138 KB), pdf (106 KB)
  24. B. Davis, C. Gauthier, P. Parakh, T. Basso, C. Lefurgy, R. Brown, and T. Mudge, "Impact of MCMs on high performance processors", Proc. ASME Advances in Electronic Packaging 97 vol. 1 (EEP-vol. 19-1), June 1997, pp. 863-868.
    ps (1 MB), pdf (55 KB)

Refereed workshop papers and posters

  1. Anshul Gandhi, Mor Harchol-Balter, Rajarshi Das, Charles Lefurgy and Jeffrey Kephart, "Power Capping Via Forced Idleness", Workshop on Energy Efficient Design, June 2009.
    Paper: PDF
    Slides: PPTX
  2. Madhu Saravana Sibi Govindan, Charles Lefurgy and Ajay Dholakia, "Using on-line power modeling for server power capping", Workshop on Energy Efficient Design, June 2009.
    Paper: PDF
    Slides: PDF
  3. Jian Li, Lixin Zhang, Charles Lefurgy, Richard Treumann, Wolfgang E. Denzei, "Thrifty Interconnection Network for HPC Systems", Poster, International Conference on Supercomputing, June 2009.
    Poster abstract: PDF
  4. Hai Huang, Kang G. Shin, Charles Lefurgy, Karthick Rajamani, Tom Keller, Eric Van Hensbergen, and Freeman Rawson, "Cooperative Software-Hardware Power Management for Main Memory", published in Lecture Notes in Computer Science, Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Volume 3471, December, 2005, pages 61-77.
    Paper: PDF
    Slides: PowerPoint
    Purchase from Spring-Verlag
  5. P. Bohrer, D. Cohn, E.N. Elnozahy, T. Keller, M. Kistler, C. Lefurgy, R. Rajamony, F. Rawson, and E. V. Hensbergen, "Energy Conservation for Servers", Proceedings of the IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp. 1-4, May 2001.
    Paper: PDF

Patents

  1. Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Timothy Hallett, Charles Lefurgy, Karthick Rajamani, Guillermo Silva, and Greg Still, Computing system voltage control, U.S. Patent 9323301, 2016.
  2. Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Timothy Hallett, Charles Lefurgy, Karthick Rajamani, Guillermo Silva, and Greg Still, Computing system voltage control, U.S. Patent 9323300, 2016.
  3. Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Charles Lefurgy, Karthick Rajamani, and Greg Still, Associating energy consumption with a virtual machine, U.S. Patent 9311209, 2016.
  4. Malcolm Allen-Ware, Ronald Bolam, Alan Drake, Charles Lefurgy, Barry Linder, Steven Mittl, and Karthick Rajamani, Monitoring aging of silicon in an integrated circuit device, U.S. Patent 9310424, 2016.
  5. Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Charles Lefurgy, Karthick Rajamani, and Greg Still, Associating energy consumption with a virtual machine, U.S. Patent 9304886, 2016.
  6. Malcolm Allen-Ware, Alan Drake, Timothy Hallett, Heather Hanson, Jordan Keuseman, Charles Lefurgy, Karthick Rajamani, Todd Rosedahl, and Guillermo Silva, Distributed power budgeting, U.S. Patent 9298247, 2016.
  7. Malcolm Allen-Ware, Alan Drake, Timothy Hallett, Heather Hanson, Jordan Keuseman, Charles Lefurgy, Karthick Rajamani, Todd Rosedahl, and Guillermo Silva, Distributed power budgeting, U.S. Patent 9292074, 2016.
  8. Charles Lefurgy, Registration-based remote debug watch and modify, U.S. Patent 9251038, 2016.
  9. Malcolm Allen-Ware, Timothy Hallett, Wei Huang, Charles Lefurgy, Glenn Miles, and Guillermo Silva, Distributed thermal management system for servers, U.S. Patent 9223326, 2015.
  10. Bishop Brock, Tilman Gloekler, Charles Lefurgy, and Greg Still, Computing system frequency target monitor, U.S. Patent 9218044, 2015.
  11. Nagashyamala Dhanwada, Anand Haridass, Arun Joseph, Charles Lefurgy, and Diwesh Pandey, Method for breaking down hardware power into sub-components, U.S. Patent 9217771, 2015.
  12. Malcolm Allen-Ware, John Carter, Wei Huang, Charles Lefurgy, and Guillermo Silva, Minimizing aggregate cooling and leakage power with fast convergence, U.S. Patent 9141159, 2015.
  13. Malcolm Allen-Ware, John Carter, Wei Huang, Charles Lefurgy, and Guillermo Silva, Minimizing aggregate cooling and leakage power with fast convergence, U.S. Patent 9146597, 2015.
  14. Charles Lefurgy, Freeman Rawson III, and Guillermo Silva, Management of thermal condition in a data processing system by dynamic management of thermal loads, U.S. Patent 8856567, 2014.
  15. Malcolm Allen-Ware, John Carter, Heather Hanson, Wei Huang, Charles Lefurgy, and Karthick Rajamani, Performance of digital circuits using current management, U.S. Patent 8779846, 2014.
  16. Malcolm Allen-Ware, Ronald Bolam, Alan Drake, Charles Lefurgy, Barry Linder, Steven Mittl, and Karthick Rajamani, Managing aging of silicon in an integrated circuit device, U.S. Patent 8713490, 2014.
  17. Heather Hanson, Charles Lefurgy, Karthick Rajamani, Freeman Rawson III, Malcolm Allen-Ware, Priority-based power capping in data processing systems, U.S. Patent 8707074, 2014.
  18. Thomas Brey, Wesley Felter, Sumeet Kochar, Charles Lefurgy, Ryuji Orita, Freeman Rawson III, and Malcolm Allen-Ware, Managing power consumption of a computer, U.S. Patent 8677160, 2014.
  19. Charles Lefurgy, Registration-based remote debug watch and modify, U.S. Patent 8589887, 2013.
  20. Richard Arndt, Heather Hanson, Charles Lefurgy, Karthick Rajamani, Freeman Rawson III, and Malcolm Allen-Ware, Allocation of energy budgets to individual partitions, U.S. Patent 8689556, 2013.
  21. Bishop Brock, John Carter, Alan Drake, Michael Floyd, Charles Lefurgy, Malcolm Allen-Ware, Performance control of frequency-adapting processors by voltage domain adjustment, U.S. Patent 8527801, 2013.
  22. Charles Lefurgy and Freeman Rawson III, Matching systems with power and thermal domains, U.S. Patent 8495554, 2013.
  23. Charles Lefurgy and Freeman Rawson III, Matching systems with power and thermal domains, U.S. Patent 8448108, 2013.
  24. Heather Hanson, Charles Lefurgy, Karthick Rajamani, Freeman Rawson III, Malcolm Allen-Ware, Priority-based power capping in data processing systems, U.S. Patent 8276012, 2012.
  25. Thomas Brey, Wesley Felter, Sumeet Kochar, Charles Lefurgy, Ryuji Orita, Freeman Rawson, Malcolm Ware, Managing power consumption of a computer, U.S. Patent 8103884, 2012.
  26. Tyler Bletsch, Ajay Dholakia, Wesley Felter, and Charles Lefurgy, Estimating power consumption of computing components configured in a computing system , U.S. Patent 8041521, 2011.
  27. Charles Lefurgy and Malcolm Allen-Ware, Attributing energy consumption to individual code threads in a data processing system, U.S. Patent 8015566, 2011.
  28. Tom Keller, Charles Lefurgy, and Hai Huang, Method and system for decreasing power consumption in memory arrays having usage-driven power management, U.S. Patent 8010764, 2011.
  29. Vivek Kashyap, Charles Lefurgy, and Dipankar Sarma, Method for power capping with co-operative dynamic voltage and frequency scaling via shared p-state table, U.S. Patent 8001402, 2011.
  30. Tyler K. Bletsch, Wesley M. Felter, Neven A. Gazala, Tibor Horvath, Charles R. Lefurgy, Method for equalizing performance of computing components, U.S. Patent 7979729, 2011.
  31. Wes Felter, Charles Lefurgy, and Tyler Bletsch, Method and system for estimating processor utilization from power measurements, U.S. Patent 7,925,901, 2011.
  32. Charles Lefurgy and Mahdu Saravana Sibi Govindan, Method and system for real time prediction of a power usage for a change to another performance state, U.S. Patent 7,904,287, 2011.
    On USPTO website
  33. Wesley M. Felter and Charles R. Lefurgy, Method and system for associating power consumption of a server with a network address assigned to the server , U.S. Patent 7,783,910, 2010.
    On USPTO website
  34. Tom Brey, Wesley Felter, Sumeet Kochar, Charles Lefurgy, Malcolm Ware, Christopher Wood, Control systems and method using a shared component actuator , U.S. Patent 7,792,597, 2010.
    On USPTO website
  35. Peter Altevogt, Hans Boettiger, Wesley Felter, Charles Lefurgy, Lutz Stiege, and Malcolm Ware, Method for autonomous dynamic voltage and frequency scaling of microprocessors , U.S. Patent 7,840,825, 2010.
    On USPTO website
  36. Tom Brey, Wes Felter, Charles Lefurgy, Karthick Rajamani, Juan Rubio, and Malcolm Ware, Method and System for Providing Performance Estimations for a Specified Power Budget, U.S. Patent 7,272,517, 2007.
    On USPTO website
  37. Tom Brey, Charles Lefurgy, Mark Rinaldi, and Malcolm Ware, Histogram Difference Method and System for Power Performance Measurement and Management, U.S. Patent 7,260,487, 2007.
    On USPTO website
  38. C. Lefurgy and E. Van Hensbergen, Method and system for power management including local bounding of device group power consumption , U.S. Patent 7,155,623, December 16, 2006.
    On USPTO website
  39. P. Bohrer and C. Lefurgy, Energy caching for a computer, U.S. Patent 6,966,005, November 15, 2005.
    On USPTO website
  40. P. Bohrer, E. Elnozahy, C. Lefurgy, R. Rajamony, B. Smith, Data storage on a multi-tiered disk system, U.S. Patent 6,925,529, August 2, 2005.
    On USPTO website

Technical reports

  1. Anshul Gandhi, Mor Harchol-Balter, Rajarshi Das, and Charles Lefurgy, "Optimal Power Allocation in Server Farms", Carnegie Mellon University Techical Report CMU-CS-09-113, March 2009.
    Paper: PDF
  2. Xiaorui Wang, Charles Lefurgy, and Malcolm Ware,"Managing Peak System-level Power with Feedback Control", IBM Research Technical Report RC23835, 2005.
    Paper: PDF
  3. Rajagopalan Desikan, Charles R. Lefurgy, Stephen W. Keckler, and Doug Burger, On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories, Technical Report TR-02-47, Department of Computer Sciences, The University of Texas at Austin, September 27, 2002.
    Paper: PDF
    Paper: PS
    Slides: PowerPoint
  4. Matthew Postiff, David Greene, Charles Lefurgy, Dave Helder and Trevor Mudge. The MIRV SimpleScalar/PISA Compiler. University of Michigan EECS Department Tech. Report CSE-TR-421-00. April 2000.
    Paper: PDF
  5. Charles Lefurgy and Trevor Mudge, Code Compression for DSP, CSE-TR-380-98, University of Michigan, November 1998
    PDF (52 KB)
  6. Charles Lefurgy, Peter Bird, I-Cheng Chen, and Trevor Mudge, Improving Code Density Using Compression Techniques, CSE-TR-342-97, July 1997.
    ps.Z (81 KB), pdf (96 KB)

Invited papers, tutorials, and talks

  1. Ibrahim Elfadel, Charles Lefurgy, Sherief Reda, and Ayse Coskun, “Avoiding Core Meltdown! – Adaptive Techniques for Power and Thermal Management of Multi-Core Processors”, Tutorial, Design Automation Conference (DAC), 2013.
    Slides (Lefurgy's section only): PDF
  2. Charles Lefurgy, “Active Management of Timing Guardband to Save Energy in POWER7”, Guest speaker, IEEE CTS CEDA, Sept. 24, 2012.
  3. Charles Lefurgy, “Active Management of Timing Guardband to Save Energy in POWER7”, Computer Architecture Seminar Series (Prof. Vijay Reddi), U. Texas, Feb. 21, 2012.
  4. Charles Lefurgy, Malcolm Allen-Ware, John Carter, Wael El-Essawy, Wes Felter, Alexandre Ferreira, Wei Huang, Anthony Hylick, Tom Keller, Karthick Rajamani, Freeman Rawson, and Juan Rubio, Energy-Efficient Data Centers and Systems, Tutorial, Presented at 2011 IEEE International Symposium on Workload Characterization, November 6, 2011.
    Slides: PDF
  5. Charles Lefurgy, "Computer System Energy Management", Keynote, The First International Workshop on Power Measurement and Profiling (PMP 2011), July 2011.
    Slides: PDF
  6. Charles Lefurgy, Malcolm Allen-Ware, John Carter, Wael El-Essawy, Wes Felter, Alexandre Ferreira, Wei Huang, Anthony Hylick, Tom Keller, Karthick Rajamani, Freeman Rawson, and Juan Rubio, Energy-Efficient Data Centers and Systems, Tutorial, Presented at 2011 IEEE International Symposium on Performance Analysis of Systems and Software, April 10 2011.
    Slides: PDF
  7. Michael Floyd, Bishop Brock, Malcolm Ware, Karthick Rajamani, Alan Drake, Charles Lefurgy, and Lorena Pesantez, "Adaptive Energy Management Features of the POWER7 Processor", HOT CHIPS 22, 2010.
    Slides: PDF
    Video: Youtube
  8. P. Bohrer, M. Elnozahy, A. Gheith, C. Lefurgy, T. Nakra, J. Peterson, R. Rajamony, R. Rockhold, H. Shafi, R. Simpson, E. Speight, K. Sudeep, E. Van Hensbergen, and Lixin Zhang, "Mambo -- A Full System Simulator for the PowerPC Architecture", ACM SIGMETRICS Performance Evaluation Review, Volume 31, Number 4, March 2004.
    Paper: PDF
  9. Karthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan C Rubio, Heather Hanson, and Tom Keller, "Power Management for Computer Systems and Datacenters", Tutorial, The 14th International Symposium on High-Performance Computer Architecture (HPCA), 2008.
    Slides: PDF
  10. Karthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan C Rubio, Heather Hanson, and Tom Keller, "Power Management for Computer Systems and Datacenters", Tutorial, International Symposium on Low Power Electronics and Design (ISLPED), 2008.
    Slides: PDF
  11. Charles Lefurgy, "Power Management for Computer Systems and Datacenters", Guest lecture, Enterprise Systems course EECS 598 Winter 2008 (Professor Thomas Wenisch), University of Michigan, March 2008.
    Slides: PDF
  12. Charles Lefurgy, "Code Compression", Guest lecture, Information Theory course EE381K-7 (Professor Sriram Vishwanath), University of Texas, March 23, 2005.
    Slides: PDF
  13. Charles Lefurgy, Super-Dense Servers: An Energy-efficient Approach to Large-Scale Server Clusters, presentation for graduate seminar, Department of Computer Science, Texas A&M University, November 2002.
    Slides: PDF

News and press releases

  1. "Self-protecting Microprocessor Saves Energy", IBM Research blog, February 29, 2012. Link

Dissertation

  1. Charles Lefurgy, Efficient Execution of Compressed Programs, Doctoral Dissertation, University of Michigan, June 2000.
    Dissertation: PDF
    Dissertation: PS
    Abstract: PDF
    Abstract: PS
    Slides: PDF
    Slides: PS
    Simulation software (used for all experiments)
  2. Charles Lefurgy, Space-efficient Executable Program Representations for Embedded Microprocessors, Thesis Proposal, April 1998.
    ps.Z (396 KB), pdf (193 KB)

 

Chronological order

2016

  • Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Timothy Hallett, Charles Lefurgy, Karthick Rajamani, Guillermo Silva, and Greg Still, Computing system voltage control, U.S. Patent 9323301, 2016.
  • Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Timothy Hallett, Charles Lefurgy, Karthick Rajamani, Guillermo Silva, and Greg Still, Computing system voltage control, U.S. Patent 9323300, 2016.
  • Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Charles Lefurgy, Karthick Rajamani, and Greg Still, Associating energy consumption with a virtual machine, U.S. Patent 9311209, 2016.
  • Malcolm Allen-Ware, Ronald Bolam, Alan Drake, Charles Lefurgy, Barry Linder, Steven Mittl, and Karthick Rajamani, Monitoring aging of silicon in an integrated circuit device, U.S. Patent 9310424, 2016.
  • Malcolm Allen-Ware, Bishop Brock, Tilman Gloekler, Charles Lefurgy, Karthick Rajamani, and Greg Still, Associating energy consumption with a virtual machine, U.S. Patent 9304886, 2016.
  • Malcolm Allen-Ware, Alan Drake, Timothy Hallett, Heather Hanson, Jordan Keuseman, Charles Lefurgy, Karthick Rajamani, Todd Rosedahl, and Guillermo Silva, Distributed power budgeting, U.S. Patent 9298247, 2016.
  • Malcolm Allen-Ware, Alan Drake, Timothy Hallett, Heather Hanson, Jordan Keuseman, Charles Lefurgy, Karthick Rajamani, Todd Rosedahl, and Guillermo Silva, Distributed power budgeting, U.S. Patent 9292074, 2016.
  • Charles Lefurgy, Registration-based remote debug watch and modify, U.S. Patent 9251038, 2016.

2015

  • Yazhou Zu, Charles Lefurgy, Jingwen Leng, Matthew Halpern, Michael Floyd, and Vijay Janapa Reddi, "Adaptive guardband scheduling to improve system-level efficiency of the POWER7+", Proceedings of the 48th International Symposium on Microarchitecture, pp. 308-321, 2015.
    Paper: PDF
  • Arun Joseph, Anand Haridass, Charles Lefurgy, Sreekanth Pai, Spandana Rachamalla, and Francesco Campisano, "FreqLeak: A frequency step based method for efficient leakage power characterization in a system", 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 195-200, 2015.
  • Tobias Webel, Preetham Lobo, Ramon Bertran, Gerard Salem, Malcolm Allen-Ware, Richard Rizzolo, Sean Carey, Thomas Strach, Alper Buyuktosunoglu, Charles Lefurgy, Pradip Bose, Ricardo Nigaglioni, Timothy Slegel, Michael Floyd, and Brian Curran, "Robust power management in the IBM z13", IBM J. Res. & Dev., Vol. 59, No. 4/5, July/September 2015.
  • Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, and Vidushi Goyal, "FirmLeak: A framework for efficient and accurate runtime estimation of leakage power by firmware", 28th International Conference on VLSI Design (VLSID), 2015.
    Paper: PDF
    Poster: PDF
  • Malcolm Allen-Ware, Timothy Hallett, Wei Huang, Charles Lefurgy, Glenn Miles, and Guillermo Silva, Distributed thermal management system for servers, U.S. Patent 9223326, 2015.
  • Bishop Brock, Tilman Gloekler, Charles Lefurgy, and Greg Still, Computing system frequency target monitor, U.S. Patent 9218044, 2015.
  • Nagashyamala Dhanwada, Anand Haridass, Arun Joseph, Charles Lefurgy, and Diwesh Pandey, Method for breaking down hardware power into sub-components, U.S. Patent 9217771, 2015.
  • Malcolm Allen-Ware, John Carter, Wei Huang, Charles Lefurgy, and Guillermo Silva, Minimizing aggregate cooling and leakage power with fast convergence, U.S. Patent 9141159, 2015.
  • Malcolm Allen-Ware, John Carter, Wei Huang, Charles Lefurgy, and Guillermo Silva, Minimizing aggregate cooling and leakage power with fast convergence, U.S. Patent 9146597, 2015.

2014

  • Shinobu Miwa and Charles Lefurgy, "Evaluation of Core Hopping on POWER7", ACM SIGMETRICS Performance Evaluation Review, Vol. 42, Issue 3, pp. 55-60, 2014.
  • Charles Lefurgy, Freeman Rawson III, and Guillermo Silva, Management of thermal condition in a data processing system by dynamic management of thermal loads, U.S. Patent 8856567, 2014.
  • Malcolm Allen-Ware, John Carter, Heather Hanson, Wei Huang, Charles Lefurgy, and Karthick Rajamani, Performance of digital circuits using current management, U.S. Patent 8779846, 2014.
  • Subhasish Mitra, Pradip Bose, Eddie Cheng, Chen-Yong Cher, Hyeonwoo Cho, Rajan Joshi, Young Moon Kim, Charles Lefurgy, Yuhua Li, Kenneth Rodbell, Kevin Skadron, James Stathis, and Lukasz Szafaryn, "The resilience wall: Cross-layer solution strategies", Proceedings of Technical Program 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014.
  • Malcolm Allen-Ware, Ronald Bolam, Alan Drake, Charles Lefurgy, Barry Linder, Steven Mittl, and Karthick Rajamani, Managing aging of silicon in an integrated circuit device, U.S. Patent 8713490, 2014.
  • Heather Hanson, Charles Lefurgy, Karthick Rajamani, Freeman Rawson III, Malcolm Allen-Ware, Priority-based power capping in data processing systems, U.S. Patent 8707074, 2014.
  • Thomas Brey, Wesley Felter, Sumeet Kochar, Charles Lefurgy, Ryuji Orita, Freeman Rawson III, and Malcolm Allen-Ware, Managing power consumption of a computer, U.S. Patent 8677160, 2014.

2013

  • Charles Lefurgy, Registration-based remote debug watch and modify, U.S. Patent 8589887, 2013.
  • Richard Arndt, Heather Hanson, Charles Lefurgy, Karthick Rajamani, Freeman Rawson III, and Malcolm Allen-Ware, Allocation of energy budgets to individual partitions, U.S. Patent 8689556, 2013.
  • Bishop Brock, John Carter, Alan Drake, Michael Floyd, Charles Lefurgy, Malcolm Allen-Ware, Performance control of frequency-adapting processors by voltage domain adjustment, U.S. Patent 8527801, 2013.
  • Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, John Carter, and Robert Berry Jr., "Active Guardband Management in POWER7+ to Save Energy and Maintain Reliability", Micro, IEEE, Vol. 33, No. 4, pp. 35-45, Aug.-Sept., 2013.
    Paper: PDF
  • Ibrahim Elfadel, Charles Lefurgy, Sherief Reda, and Ayse Coskun, “Avoiding Core Meltdown! – Adaptive Techniques for Power and Thermal Management of Multi-Core Processors”, Tutorial, Design Automation Conference (DAC), 2013.
    Slides (Lefurgy's section only): PDF
  • Charles Lefurgy and Freeman Rawson III, Matching systems with power and thermal domains, U.S. Patent 8495554, 2013.
  • Charles Lefurgy and Freeman Rawson III, Matching systems with power and thermal domains, U.S. Patent 8448108, 2013.

2012

  • Wei Huang, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael Floyd, Karthick Rajamani, Malcolm Allen-Ware, and Bishop Brock, "Accurate Fine-Grained Processor Power Proxies", Proceedings of the 45th Annual International Symposium on Microarchitecture, December 2012. (Acceptance rate: 40/228 = 17.5%)
    Paper: PDF
    Slides: PDF
    Poster: PDF
    Summary slide: PDF
  • Heather Hanson, Charles Lefurgy, Karthick Rajamani, Freeman Rawson III, Malcolm Allen-Ware, Priority-based power capping in data processing systems, U.S. Patent 8276012, 2012.
  • Charles Lefurgy, “Active Management of Timing Guardband to Save Energy in POWER7”, Guest speaker, IEEE CTS CEDA, Sept. 24, 2012.
  • "Self-protecting Microprocessor Saves Energy", IBM Research blog, February 29, 2012. Link
  • Charles Lefurgy, “Active Management of Timing Guardband to Save Energy in POWER7”, Computer Architecture Seminar Series (Prof. Vijay Reddi), U. Texas, Feb. 21, 2012.
  • Thomas Brey, Wesley Felter, Sumeet Kochar, Charles Lefurgy, Ryuji Orita, Freeman Rawson, Malcolm Ware, Managing power consumption of a computer, U.S. Patent 8103884, 2012.
  • Xiaorui Wang, Ming Chen, Charles Lefurgy, and Tom Keller, "SHIP: A Scalable Hierarchical Power Control Architecture for Large-Scale Data Centers ", IEEE Trans. on Parallel and Distributed Systems, 23(1): 168-176, January 2012. (Spotlight paper of the issue)
    Paper: PDF
    Supplementary Paper: PDF

2011

  • Charles Lefurgy, Alan Drake, Michael Floyd, Malcolm Allen-Ware, Bishop Brock, Jose Tierno, and John Carter, "Active Management of Timing Guardband to Save Energy in POWER7", Proceedings of the 44th Annual International Symposium on Microarchitecture, December 2011. MICRO-44 Best Paper Award. IBM Pat Goldberg Memorial Best Paper Award for 2011. (Acceptance rate: 44/209 = 21%)
    Paper: PDF
    Slides: PDF
    Video: WMV
  • Charles Lefurgy, Malcolm Allen-Ware, John Carter, Wael El-Essawy, Wes Felter, Alexandre Ferreira, Wei Huang, Anthony Hylick, Tom Keller, Karthick Rajamani, Freeman Rawson, and Juan Rubio, Energy-Efficient Data Centers and Systems, Tutorial, Presented at 2011 IEEE International Symposium on Workload Characterization, November 6, 2011.
    Slides: PDF
  • Tyler Bletsch, Ajay Dholakia, Wesley Felter, and Charles Lefurgy, Estimating power consumption of computing components configured in a computing system , U.S. Patent 8041521, 2011.
  • Charles Lefurgy and Malcolm Allen-Ware, Attributing energy consumption to individual code threads in a data processing system, U.S. Patent 8015566, 2011.
  • Tom Keller, Charles Lefurgy, and Hai Huang, Method and system for decreasing power consumption in memory arrays having usage-driven power management, U.S. Patent 8010764, 2011.
  • Vivek Kashyap, Charles Lefurgy, and Dipankar Sarma, Method for power capping with co-operative dynamic voltage and frequency scaling via shared p-state table, U.S. Patent 8001402, 2011.
  • Charles Lefurgy, "Computer System Energy Management", Keynote, The First International Workshop on Power Measurement and Profiling (PMP 2011), 2011.
    Slides: PDF
  • Xing Fu, Xiaorui Wang, and Charles Lefurgy, "How Much Power Oversubscription is Safe and Allowed in Data Centers?", The 8th International Conference on Autonomic Computing (ICAC 2011), Karlsruhe, Germany, June 2011. (Acceptance rate: 20/89 = 22%)
    Paper: PDF
    Slides: PDF
  • Wei Huang, Malcolm Allen-Ware, John B. Carter, Elmootazbellah Elnozahy, Hendrik Hamann, Tom Keller, Charles Lefurgy, Jian Li, Karthick Rajamani, and Juan Rubio, "TAPO: Thermal-Aware Power Optimization Techniques for Servers and Data Centers", International Green Computing Conference (IGCC'11), 2011. (Acceptance rate: 26/85 = 31%)
    Best paper award
    Paper: PDF
    Slides: PDF
  • Tyler K. Bletsch, Wesley M. Felter, Neven A. Gazala, Tibor Horvath, Charles R. Lefurgy, Method for equalizing performance of computing components, U.S. Patent 7979729, 2011.
  • Charles Lefurgy, Malcolm Allen-Ware, John Carter, Wael El-Essawy, Wes Felter, Alexandre Ferreira, Wei Huang, Anthony Hylick, Tom Keller, Karthick Rajamani, Freeman Rawson, and Juan Rubio, Energy-Efficient Data Centers and Systems, Tutorial, Presented at 2011 IEEE International Symposium on Performance Analysis of Systems and Software, April 10 2011.
    Slides: PDF
  • Wes Felter, Charles Lefurgy, and Tyler Bletsch, Method and system for estimating processor utilization from power measurements, U.S. Patent 7925901, 2011.
  • Charles Lefurgy and Mahdu Saravana Sibi Govindan, Method and system for real time prediction of a power usage for a change to another performance state, U.S. Patent 7904287, 2011.
  • Jian Li, Lixin Zhang, Charles Lefurgy, Wei Huang, Wolfgang Denzel, Richard Treumann, and Kun Wang, "Power Shifting in Thrifty Interconnection Network ", Proceedings of the 17th International Symposium on High-Performance Computer Architecture (HPCA), 2011. (Acceptance rate: 42/227 ˜ 18.5%)
    Paper: PDF
    Slides: PDF
  • Michael Floyd, Bishop Brock, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, Jose A. Tierno, Pradip Bose, and Alper Buyuktosunoglu, "Introducing the Adaptive Energy Management Features of the POWER7 Chip ", IEEE Micro, vol. 31, no. 2, March/April, 2011.
    Paper: PDF

2010

  • Michael Floyd, Bishop Brock, Malcolm Ware, Karthick Rajamani, Alan Drake, Charles Lefurgy, and Lorena Pesantez, "Adaptive Energy Management Features of the POWER7 Processor", HOT CHIPS 22, 2010.
    Slides: PDF
  • Wesley M. Felter and Charles R. Lefurgy, Method and system for associating power consumption of a server with a network address assigned to the server , U.S. Patent 7,783,910, 2010.
    On USPTO website
  • Tom Brey, Wesley Felter, Sumeet Kochar, Charles Lefurgy, Malcolm Ware, Christopher Wood, Control systems and method using a shared component actuator , U.S. Patent 7,792,597, 2010.
    On USPTO website
  • Peter Altevogt, Hans Boettiger, Wesley Felter, Charles Lefurgy, Lutz Stiege, and Malcolm Ware, Method for autonomous dynamic voltage and frequency scaling of microprocessors , U.S. Patent 7,840,825, 2010.
    On USPTO website

2009

  • Xiaorui Wang, Ming Chen, Charles Lefurgy, and Tom W. Keller, "SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers", The Eighteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2009.
    Paper: PDF
  • Anshul Gandhi, Mor Harchol-Balter, Rajarshi Das, and Charles Lefurgy, "Optimal Power Allocation in Server Farms", Proceedings of ACM SIGMETRICS 2009 Conference on Measurement and Modeling of Computer Systems. Seattle, WA, June 2009. (Acceptance rate: 27/180 = 15%)
    Paper: PDF
    Tech report: PDF (additional details)
    Slides: PPT
  • Anshul Gandhi, Mor Harchol-Balter, Rajarshi Das, Charles Lefurgy and Jeffrey Kephart, "Power Capping Via Forced Idleness", Workshop on Energy Efficient Design, June 2009.
    Paper: PDF
    Slides: PPTX
  • Madhu Saravana Sibi Govindan, Charles Lefurgy and Ajay Dholakia, "Using on-line power modeling for server power capping", Workshop on Energy Efficient Design, June 2009.
    Paper: PDF
    Slides: PDF
  • Jian Li, Lixin Zhang, Charles Lefurgy, Richard Treumann, Wolfgang E. Denzei, "Thrifty Interconnection Network for HPC Systems", Poster, International Conference on Supercomputing, June 2009.
    Poster abstract: PDF
  • Anshul Gandhi, Mor Harchol-Balter, Rajarshi Das, and Charles Lefurgy, "Optimal Power Allocation in Server Farms", Carnegie Mellon University Techical Report CMU-CS-09-113, March 2009.
    Paper: PDF

2008

  • Rajarshi Das, Jeffrey O. Kephart, Charles Lefurgy, Gerald Tesauro, David W. Levine, and Hoi Chan, "Autonomic Multi-Agent Management of Power and Performance in Data Centers", The 7th International Conference on Autonomous Agents and Multiagent Systems (AAMAS), 2008.
    Paper: PDF
  • Karthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan C Rubio, Heather Hanson, and Tom Keller, "Power Management for Computer Systems and Datacenters", Tutorial, The 14th International Symposium on High-Performance Computer Architecture (HPCA), 2008.
    Slides: PDF
  • Karthick Rajamani, Charles Lefurgy, Soraya Ghiasi, Juan C Rubio, Heather Hanson, and Tom Keller, "Power Management for Computer Systems and Datacenters", Tutorial, International Symposium on Low Power Electronics and Design (ISLPED), 2008.
    Slides: PDF
  • Charles Lefurgy, "Power Management for Computer Systems and Datacenters", Guest lecture, Enterprise Systems course EECS 598 Winter 2008, University of Michigan, March 2008.
    Slides: PDF

2007

  • Gerald Tesauro, Rajarshi Das, Hoi Chan, Jeffrey Kephart, David Levine, Freeman Rawson, and Charles Lefurgy, "Managing Power Consumption and Performance of Computing Systems Using Reinforcement Learning", Proceedings of the Neural Information Processing Systems Conference (NIPS), 2007.
    Paper: PDF
    Slide: PDF
  • Charles Lefurgy, Xiaorui Wang, and Malcolm Ware, "Power capping: a prelude to power shifting", Cluster Computing, Springer Netherlands, November 2007.
    Paper: PDF
    On Springer website

  • Tom Brey, Wes Felter, Charles Lefurgy, Karthick Rajamani, Juan Rubio, and Malcolm Ware, Method and System for Providing Performance Estimations for a Specified Power Budget, U.S. Patent 7,272,517, 2007.
    On USPTO website
  • Tom Brey, Charles Lefurgy, Mark Rinaldi, and Malcolm Ware, Histogram Difference Method and System for Power Performance Measurement and Management, U.S. Patent 7,260,487, 2007.
    On USPTO website
  • Charles Lefurgy, Xiaorui Wang, and Malcolm Ware, "Server-level Power Control ", 4th IEEE Conference on Autonomic Computing (ICAC'07), 2007.
    Paper: PDF
    Slides: PDF

    Abstract: We present a technique that controls the peak power consumption of a high-density server by implementing a feedback controller that uses precise, system-level power measurement to periodically select the highest performance state while keeping the system within a fixed power constraint. A control theoretic methodology is applied to systematically design this control loop with analytic assurances of system stability and controller performance, despite unpredictable workloads and running environments. In a real server we are able to control power over a 1 second period to within 1 W. Additionally, we have observed that power over an 8 second period can be controlled to within 0.1 W. We believe that we are the first to demonstrate such precise control of power in a real server.

    Conventional servers respond to power supply constraint situations by using simple open-loop policies to set a safe performance level in order to limit peak power consumption. We show that closed-loop control can provide higher performance under these conditions and test this technique on an IBM BladeCenter HS20 server. Experimental results demonstrate that closed-loop control provides up to 82% higher application performance compared to open-loop control and up to 17% higher performance compared to a widely used ad-hoc technique.
  • Jeffrey O. Kephart, Hoi Chan, Rajarshi Das, David W. Levine, Gerald Tesauro, Freeman Rawson, and Charles Lefurgy , "Coordinating multiple autonomic managers to achieve specified power-performance tradeoffs", 4th IEEE Conference on Autonomic Computing (ICAC'07), 2007.
    Paper: PDF
    Slides: PDF

    Abstract: Getting multiple autonomic managers to work together towards a common goal is a significant architectural and algorithmic challenge, as noted in the ICAC 2006 panel discussion regarding “Can we build effective multi-vendor autonomic systems?” We address this challenge in a real small-scale system that processes web transactions. An administrator uses a utility function to define a set of power and performance objectives. Rather than creating a central controller to manage performance and power simultaneously, we use two existing IBM products, one that manages performance and one that manages power by controlling clock frequency. We demonstrate that, with good architectural and algorithmic choices established through trial and error, the two managers can indeed work together to act in accordance with a flexible set of power-performance objectives and tradeoffs, resulting in power savings of approximately 10%. Key elements of our approach include a) a feedback controller that establishes a power cap (a limit on consumed power) by manipulating clock frequency and b) reinforcement learning, which adaptively learns models of the dependence of performance and power consumption on workload intensity and the powercap.

2006

  • C. Lefurgy and E. Van Hensbergen, Method and system for power management including local bounding of device group power consumption , U.S. Patent 7,155,623, December 16, 2006.
    On USPTO website

2005

  • Xiaorui Wang, Charles Lefurgy, and Malcolm Ware,"Managing Peak System-level Power with Feedback Control", IBM Research Technical Report RC23835, 2005.
    Paper: PDF

    Abstract: Power consumption has arguably become the most important design consideration for modern, high-density servers, but current power management implementations have not evolved beyond primitive responses to thermal emergencies and do not manage to varying power and cooling constraints.

    We present a technique that manages the peak power consumption of a high-density server by implementing a feedback controller that uses precise, system-level power measurement to periodically select the highest performance state while keeping the system within a fixed power constraint. A control theoretic methodology is applied to systematically design this control loop with analytic assurances of system stability and controller performance, despite unpredictable workloads and running environments.

    This technique is particularly valuable when applied to servers with multiple power supplies, where a partial failure of the power supply subsystem can result in a loss of performance in order to meet a lower power constraint. Conventional servers use simple open-loop policies to set a safe performance level in order to limit peak power consumption. We show that closed-loop control can provide a more graceful degradation of service under these conditions and test this technique on an IBM BladeCenter HS20 server. Experimental results demonstrate that closed-loop control provides superior application performance compared to open-loop policies.

  • P. Bohrer and C. Lefurgy, Energy caching for a computer, U.S. Patent 6,966,005, November 15, 2005.
    On USPTO website
  • P. Bohrer, E. Elnozahy, C. Lefurgy, R. Rajamony, B. Smith, Data storage on a multi-tiered disk system, U.S. Patent 6,925,529, August 2, 2005.
    On USPTO website
  • Hai Huang, Charles Lefurgy, Tom Keller, and Kang G. Shin, "Improving Energy Efficiency by Making DRAM Less Randomly Accessed", in Proceedings of the International Symposium on Low-Power Electronics and Design (ISLPED), August, 2005.
    Paper: PDF
    Paper: PS
    Slides: PowerPoint

    Abstract: Existing techniques manage power for the main memory by passively monitoring the memory traffic, and based on which, predict when to power down and into which low-power state to transition. However, passively monitoring the memory traffic can be far from being effective as idle periods between consecutive memory accesses are often too short for existing power-management techniques to take full advantage of the deeper power-saving state implemented in modern DRAM architectures. In this paper, we propose a new technique that will actively reshape the memory traffic to coalesce short idle periods — which were previously unusable for power management — into longer ones, thus enabling existing techniques to effectively exploit idleness in the memory.

2004

  • Hai Huang, Kang G. Shin, Charles Lefurgy, Karthick Rajamani, Tom Keller, Eric Van Hensbergen, and Freeman Rawson, "Cooperative Software-Hardware Power Management for Main Memory", published in Lecture Notes in Computer Science, Power-Aware Computer Systems: 4th International Workshop, PACS 2004, Volume 3471, December, 2005, pages 61-77.
    Paper: PDF
    Slides: PowerPoint
    Purchase from Spring-Verlag

    Abstract: Energy is becoming a critical resource to not only small battery-powered devices but also large server systems, where high energy consumption translates to excessive heat dissipation, which, in turn, increases cooling costs and causes servers to become more prone to failure. Main memory is one of the most energy-consuming components in many systems. In this paper, we propose and evaluate a novel power management technique, in which the system software provides the memory controller with a small amount of information about the current state of the system, which is used by the memory controller to significantly reduce power. Our technique enables the memory controller to more intelligently react to the changing state in the system, and therefore, be able to make more accurate and more aggressive power management decisions. The proposed technique is evaluated against previously-implemented power management techniques running synthetic, SPECjbb2000 and various SPECcpu2000 benchmarks. Using SPEC benchmarks, we are able to show that the cooperative technique consumes 14.2–17.3% less energy than the previously-proposed hardware-only technique, 16.0–25.8% less than the software-only technique, and 71.6– 75.8% less than no power management.
  • Juan Rubio, Charles Lefurgy, and Lizy K. John, "Improving Server Performance on Transaction Processing Workloads by Enhanced Data Placement", Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'04), October, 2004, pp. 84-91.
    Paper: PDF
    Slides: PowerPoint

    Abstract: Modern servers access large volumes of data while running commercial workloads. The data is typically spread among several storage devices (e.g. disks). Carefully placing the data across the storage devices can minimize costly remote accesses and improve performance.

    We propose the use of simulated annealing to arrive at an effective layout of data on disk. The proposed technique considers the configuration of the system and the cost of data movement. An initial layout globally optimized across all queries, shows speedups of up to 13% for a group of DSS queries and up to 6% for selected OLTP queries.

    This technique can be re-applied at run-time to further improve performance beyond the initial, globally optimized data layout. This scheme monitors architecture parameters to prevent optimizations of multiple operations to conflict with each other. Such a dynamic reorganization results in speedups of up to 23% for the DSS queries and up to 10% for the OLTP queries.

  • P. Bohrer, M. Elnozahy, A. Gheith, C. Lefurgy, T. Nakra, J. Peterson, R. Rajamony, R. Rockhold, H. Shafi, R. Simpson, E. Speight, K. Sudeep, E. Van Hensbergen, and Lixin Zhang, "Mambo -- A Full System Simulator for the PowerPC Architecture", ACM SIGMETRICS Performance Evaluation Review, Volume 31, Number 4, March 2004.
    Paper: PDF

    Abstract: Mambo is a full-system simulator for modeling PowerPC-based systems. It provides building blocks for creating simulators that range from purely functional to timing-accurate. Functional versions support fast emulation of individual PowerPC instructions and the devices necessary for executing operating systems. Timing-accurate versions add the ability to account for device timing delays, and support the modeling of the PowerPC processor microarchitecture. We describe our experience in implementing the simulator and its uses within IBM to model future systems, support early software development, and design new system software.

2003

  • Charles Lefurgy, Karthick Rajamani, Freeman Rawson, Wes Felter, Michael Kistler, Tom W. Keller, "Energy Management for Commercial Servers", IEEE Computer, pp. 39-48, December, 2003.
    Paper: PDF

    Abstract: Until recently, commercial servers had little need for aggressive energy management approaches unlike embedded and mobile computers. But, the tremendous growth in transistor densities and scale of computing have brought up difficult energy management problems for server systems. Techniques discussed here provide new power-conserving solutions appropriate for commercial server environments.
  • W.M. Felter, T.W. Keller, M.D. Kistler, C. Lefurgy, K. Rajamani, R. Rajamony, F.L. Rawson, B.A. Smith, and E. van Hensbergen, "On the performance and use of dense servers", IBM Journal of R & D, vol. 47, no. 5/6, pp. 671-688, Sept.-Nov., 2003.
    Paper: PDF

    Abstract: Dense servers trade performance at the node level for higher deployment density and lower power consumption as well as the possibility of reduced cost of ownership. System performance and the details of energy consumption for this class of servers, however, are not well understood. In this paper, we describe a research prototype designated as the Super Dense Server (SDS), which was optimized for high-density deployment. We describe its hardware features, show how they challenge the operating system and middleware, and describe how we have enhanced its software to handle these challenges. Our performance evaluation has shown that dense servers are a viable deployment alternative for the edge and application servers commonly found at conventional Web sites and large data centers. Using industry benchmarks, we have shown that SDS outperforms a comparable traditional server by almost a factor of 2 for CPU-bound electronic commerce workloads for the same space and roughly equivalent power budget. We have observed the same advantage in performance when SDS is compared to the alternative solution of virtualizing a high-end server to handle “scaled-down” workloads. We have also shown that SDS offers finer power management control than traditional servers, allowing higher energy efficiency per unit of computation. However, for high-intensity Web-serving workloads, SDS does not perform as well as a traditional server when many nodes must be configured into a cluster to provide a single system image. In that case, the limited memory of each SDS node reduces its performance scalability, and a traditional server is a better alternative. We have concluded that until technology advances allow denser packaging of memory or more efficient use of memory across nodes, the best performance and energy efficiency can be obtained by heterogeneous deployment of both traditional high-end and dense servers.

     

  • Karthick Rajamani and Charles Lefurgy, "On Evaluating Request-Distribution Schemes for Saving Energy in Server Clusters", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'03), March 2003.
    Paper: PDF
    Paper: PS
    Slides: PDF

    Abstract: Power-performance optimization is a relatively new problem area particularly in the context of server clusters. Power-aware request distribution is a method of scheduling service requests among servers in a cluster so that energy consumption is minimized, while maintaining a particular level of performance. Energy efficiency is obtained by powering-down some servers when the desired quality of service can be met with fewer servers. We have found that it is critical to take into account the system and workload factors during both the design and the evaluation of such request distribution schemes. We identify the key system and workload factors that impact such policies and their effectiveness in saving energy. We measure a web cluster running an industry-standard commercial web workload and demonstrate that understanding the identified system-workload context is critical to performing valid evaluations and even for improving the energy-saving schemes.

2002

  • Charles Lefurgy, Super-Dense Servers: An Energy-efficient Approach to Large-Scale Server Clusters, presentation for graduate seminar, Department of Computer Science, Texas A&M University, November 2002.
    Slides: PDF

    Abstract: At IBM Research in Austin, we have investigated the problem of designing a web server cluster that can be used in high-volume deployments that are limited by energy and cooling constraints. First we designed a cluster using a custom-designed Super Dense Server built from low-power components that are normally used in mobile systems. Second, we improved the energy-efficiency of the cluster further by developing software techniques for power-management. Energy is saved by powering-down some servers when the desired quality of service can be met with fewer servers.

    In the first half of this talk, I will describe the research prototype Super Dense Server. I will cover its hardware features, show how they challenge the operating system and middleware and describe the system software enhancements used to meet these challenges. The performance evaluation shows that dense servers are a viable deployment alternative for the edge and application servers commonly found in conventional web sites and large data centers. In the second half of the talk, I will describe a method of distributing web requests across the cluster so that energy can be saved at a small cost in performance. This will cover the common pitfalls in doing energy measurement studies, the modifications required to enable the power-aware request distribution, and results on the energy savings achieved.

  • Rajagopalan Desikan, Charles R. Lefurgy, Stephen W. Keckler, and Doug Burger, On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories, Technical Report TR-02-47, Department of Computer Sciences, The University of Texas at Austin, September 27, 2002.
    Paper: PDF
    Paper: PS
    Slides: PowerPoint

    Abstract: Impediments to main memory performance have traditionally been due to the divergence in processor versus memory speed and the pin bandwidth limitations of modern packaging technologies. In this paper we evaluate a magneto-resistive memory (MRAM)-based hierarchy to address these future constraints. MRAM devices are nonvolatile, and have the potential to be faster than DRAM, denser than embedded DRAM, and can be integrated into the processor die in layers above those of conventional wiring. We describe basic MRAM device operation, develop detailed models for MRAM banks and layers, and evaluate an MRAM-based memory hierarchy in which all off-chip physical DRAM is replaced by on-chip MRAM. We show that this hierarchy offers extremely high bandwidth, resulting in a 15% improvement in end-program performance over conventional DRAM-based main memory systems. Finally, we compare the MRAM hierarchy to one using a chipstacked DRAM technology and show that the extra bandwidth of MRAM enables it to outperform this nearer-term technology. We expect that the advantage of MRAM-like technologies will increase with the proliferation of chip multiprocessors due to increased memory bandwidth demands.
  • Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen, Ram Rajamony, and Raj Rajkumar, "Critical Power Slope: Understanding the Runtime Effects of Frequency Scaling", Proceedings of the 16th Annual ACM International Conference on Supercomputing (ICS'02), June 2002.
    Awarded Best Student Presentation (Akihiko Miyoshi).
    Paper: PDF
    Slides: Powerpoint

    Abstract: Energy efficiency is becoming an increasingly important feature for both mobile and high-performance server systems. Most processors designed today include power management features that provide processor operating points which can be used in power management algorithms. However, existing power management algorithms implicitly assume that lower performance points are more energy efficient than higher performance points. Our empirical observations indicate that for many systems, this assumption is not valid.

    We introduce a new concept called critical power slope to explain and capture the power-performance characteristics of systems with power management features. We evaluate three systems - a clock throttled Pentium laptop, a frequency scaled PowerPC platform, and a voltage scaled system to demonstrate the benefits of our approach. Our evaluation is based on empirical measurements of the first two systems, and publicly available data for the third. Using critical power slope, we explain why on the Pentium-based system, it is energy efficient to run only at the highest frequency, while on the PowerPC-based system, it is energy efficient to run at the lowest frequency point. We confirm our results by measuring the behavior of a web serving benchmark. Furthermore, we extend the critical power slope concept to understand the benefits of voltage scaling when combined with frequency scaling. We show that in some cases, it may be energy efficient not to reduce voltage below a certain point.

  • P. Bohrer, E. N. Elnozahy, T. Keller, M. Kistler, C. Lefurgy, C. McDowell, and R. Rajamony, "The Case for Power Management in Web Servers", published in Power Aware Computing, editors R. Melhem and R. Graybill, Kluwer Academic/Plenum Publishers, 2002.
    Chapter: PDF
    Order the book from Kluwer Academic/Plenum Publishers

    Abstract: Power management has traditionally focused on portable and handheld devices. This paper breaks with tradition and presents a case for managing power consumption in web servers. Web servers experience large periods of low utilization, presenting an opportunity for using power management to reduce energy consumption with minimal performance impact. We measured the energy consumption of a typical web server under a variety of workloads derived from access logs of real websites, including the 1998 Winter Olympics web site. Our measurements show that the CPU is the largest consumer of power for typical web servers today.

    We have also created a power simulator for web serving workloads that estimates CPU energy consumption with less than 5.7% error for our workloads. The simulator is fast, processing over 75,000 requests/second on a 866MHz uniprocessor machine. Using the simulator, we quantify the potential benefits of dynamically scaling the processor voltage and frequency, a power management technique that is traditionally found only in handheld devices. We find that dynamic voltage and frequency scaling is highly effective for saving energy with moderately intense web workloads, saving from 23% to 36% of the CPU energy while keeping server responsiveness within reasonable limits.

2001

  • P. Bohrer, D. Cohn, E.N. Elnozahy, T. Keller, M. Kistler, C. Lefurgy, R. Rajamony, F. Rawson, and E. V. Hensbergen, "Energy Conservation for Servers", Proceedings of the IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp. 1-4, May 2001.
    Paper: PDF

    Abstract: Power management has been thoroughly studied for applications running on battery-powered platforms. We take the position that power management is equally important for server environments, where high performance and reliability have traditionally been the most important design and evaluation factors. This position breaks with tradition and argues for considering energy consumption on the same footing. We base our opinion on several observed trends in the technology and the marketplace.

2000

  • Charles Lefurgy, Efficient Execution of Compressed Programs, Doctoral Dissertation, University of Michigan, June 2000.
    Dissertation: PDF
    Dissertation: PS
    Abstract: PDF
    Abstract: PS
    Slides: PDF
    Slides: PS
    Simulation software (used for all experiments)

    Abstract

    Chair: Trevor Mudge

    Code compression is the technique of using data compression to reduce the program memory size for memory-limited, embedded computers. For system-on-a-chip designs, this reduces the system die area which lowers die cost. After compilation, the binary (native code) program is compressed and stored in the embedded system. At run-time, the compressed program is incrementally decompressed and executed. While compressed programs have better code density, their performance is typically lower because additional effort is required to decompress the instruction stream. This dissertation presents methods to improve the performance of compressed programs.

    Decompression overhead can be minimized by using special-purpose hardware. This dissertation analyzes IBM's CodePack decompression algorithm and proposes optimizations for it. The optimized decompressor can often execute compressed programs faster than the original native program. The performance benefit of using fewer memory transactions to fetch compressed instructions surpasses the small decompression overhead. Therefore, code compression improves performance as well as code density.

    The decompression hardware can be largely replaced with software. The benefits of software decompression are greater design flexibility, reduced hardware complexity, reduced die area, and reduced cost. However, software decompression is much slower than hardware decompression. On a 5-stage pipelined embedded processor with a 4KB instruction cache, CodePack programs execute 1.3 to 27.0 times slower than native programs and reduce program memory die area (instruction cache and main memory) by 26% to 41%. This dissertation proposes instruction set support to enable efficient software-managed decompression. In addition, it explores two software optimizations, hybrid programs and memoization, to improve the execution time of compressed programs by reducing the compression. Hybrid programs contain both native and compressed code to reduce the number of times the decompressor is invoked. Memoization is a dynamic optimization that caches recent decompression results to also avoid invoking the decompressor. Optimized compressed programs that reduce die area 10% to 33% execute only 1.00 to 1.22 times slower than native code. In addition, loop-oriented (multimedia) programs are nearly as fast as native code.

  • Charles Lefurgy, Eva Piccininni, and Trevor Mudge, "Reducing Code Size with Run-time Decompression", Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA), January 2000.
    Paper: PDF
    Paper: PS
    Slides: PDF
    Slides: PS

    Abstract: Compressed representations of programs can be used to improve the code density in embedded systems. Several hardware decompression architectures have been proposed recently. In this paper, we present a method of decompressing programs using software. It relies on using a software-managed instruction cache under control of the decompressor. This is achieved by employing a simple cache management instruction that allows explicit writing into a cache line. We also consider selective compression (determining which procedures in a program should be compressed) and show that selection based on cache miss profiles can substantially outperform the usual execution time based profiles for some benchmarks.
  • Matthew Postiff, David Greene, Charles Lefurgy, Dave Helder and Trevor Mudge. The MIRV SimpleScalar/PISA Compiler. University of Michigan EECS Department Tech. Report CSE-TR-421-00. April 2000.
    Paper: PDF

1999

  • Charles Lefurgy, Eva Piccininni, and Trevor Mudge, "Analysis of a High Performance Code Compression Method", Proceedings of the 32th Annual International Symposium on Microarchitecture, pp. 93-102, November 1999.
    Paper: PDF
    Paper: PS
    Slides: PDF
    Slides: PS

    Abstract: Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal candidate for study. We find that code compression with appropriate hardware optimizations does not have to incur much performance loss. Furthermore, our studies show this holds for architectures with a wide range of memory configurations and issue widths. Surprisingly, we find that a performance increase over native code is achievable in many situations.

  • Charles Lefurgy and Trevor Mudge,"Fast Software-managed Code Decompression", Proceedings of CASES'99 (Computer and Architecture Support for Embedded Systems), pp. 139-143, October 1999.
    Presented at 10th Annual IPoCSE Review, University of Michigan
    Paper: PDF
    Paper: PS
    Slides: PDF
    Slides: PS

    Abstract: Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal candidate for study. We find that code compression with appropriate hardware optimizations does not have to incur much performance loss. Furthermore, our studies show this holds for architectures with a wide range of memory configurations and issue widths. Surprisingly, we find that a performance increase over native code is achievable in many situations.

1998

  • Charles Lefurgy and Trevor Mudge, Code Compression for DSP, CSE-TR-380-98, University of Michigan, November 1998
    PDF (52 KB)

    Abstract: Previous works have proposed adding compression techniques to a variety of architectural styles to reduce instruction memory requirements. It is not immediately clear how these results apply to DSP architectures. DSP instructions are longer and have potentially greater variation which can decrease compression ratio. Our results demonstrate that DSP programs do provide sufficient repetition for compression algorithms. We propose a compression method and apply it to SHARC, a popular DSP architecture. Even using a very simple compression algorithm, it is possible to halve the size of the instruction memory requirements.

  • Charles Lefurgy, Space-efficient Executable Program Representations for Embedded Microprocessors, Thesis Proposal, April 1998.
    ps.Z (396 KB), pdf (193 KB)

    Abstract: Both low-cost embedded systems and high-performance microprocessors can benefit from small program sizes. This thesis proposal focuses on program representations of embedded applications, where execution speed can be traded for code size. Our preliminary work borrows concepts from the field of text compression and applies them to the compression of instruction sequences. We present an experiment that examines modifications at the microarchitecture level to support compressed programs. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We demonstrate our technique by applying it to the PowerPC, ARM, i386, and MIPS-16 instruction sets. Finally, we use our results to propose another efficient program representation that explicitly communicates the patterns of computation common to each program.

1997

  • Charles Lefurgy, Peter Bird, I-Cheng Chen, and Trevor Mudge, "Improving Code Density Using Compression Techniques", Proceedings of the 30th Annual International Symposium on Microarchitecture, pp. 194-203, December 1997.
    ps.Z (138 KB), pdf (106 KB)

    Abstract: We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM, and i386 instruction sets and achieve an average size reduction of 39%, 34%, and 26%, respectively, for SPEC CINT95 programs.

  • Charles Lefurgy, Peter Bird, I-Cheng Chen, and Trevor Mudge, Improving Code Density Using Compression Techniques, CSE-TR-342-97, July 1997.
    ps.Z (81 KB), pdf (96 KB)

    Abstract: We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC instruction set and achieve 30% to 50% reduction in size for SPEC CINT95 programs.

  • B. Davis, C. Gauthier, P. Parakh, T. Basso, C. Lefurgy, R. Brown, and T. Mudge, "Impact of MCMs on high performance processors", Proc. ASME Advances in Electronic Packaging 97 vol. 1 (EEP-vol. 19-1), June 1997, pp. 863-868.
    ps (1 MB), pdf (55 KB)

    Abstract: Researchers at the University of Michigan, in collaboration with their partners from Motorola and Cascade Design Automation, are developing design methodologies and automated tools for use in implementing high clock rate digital "systems-on-an-MCM." The PUMA processor, a demonstration vehicle that executes a subset of the PowerPC instruction set, will be designed to operate with a 1 GHz clock. The PUMA will be implemented as a system-on-an-MCM from a set of complementary GaAs (CGaAs) chips that employ area interconnect for high bandwidth inter-chip connections on the MCM. In particular, the paper discusses design tools for systems-on-an-MCM, the optimization of inter-chip drivers, and techniques for optimizing the system performance given the delay of inter-chip crossing.