Alper Buyuktosunoglu  Alper Buyuktosunoglu photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA

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Professional Associations

Professional Associations:  ACM  |  Fellow, IEEE  |  IEEE   |  IEEE Computer Society


 

  1. A. Vega, A. Buyuktosunoglu, P. Bose. Secure Swarm Intelligence: A New Approach to Many-Core Power/Thermal Management. Invited Paper. International Symposium on Low Power Electronics and Design (ISLPED), July 2017.
  2. P. Bose, A. Buyuktosunoglu. Resilient, Energy-Secure Power Management. Invited Paper. International Symposium on Low Power Electronics and Design (ISLPED), July 2017.
  3. C. Ortega, M. Moreto, M. Casas, R. Bertran, A. Buyuktosunoglu, A. Eichenberger, P. Bose. libPRISM: An Intelligent Adaptation of Prefetch and SMT Levels. International Conference on Supercomputing (ICS), June 2017.
  4. P. Parida, M. Schultz, M. Gaynes, A. Sridhar, O. Ozsun, A. Vega, A. Buyuktosunoglu, T. Chainer. Thermal Model for Embedded Two-Phase Liquid Cooled Microprocessor. Outstanding Paper. Honorable Mention. The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), May 2017.
  5. P. Bose, A. Buyuktosunoglu. Architectural Support for Cognitive Processing. Guest Editors' Introduction for Special Issue on Cognitive Architectures, IEEE Micro, January/February 2017.
  6. P. Chuang, C. Vezyrtzis, D. Pathak, R. Rizzolo, T. Webel, T. Strach, O. Torreiter, P. Lobo, A. Buyuktosunoglu, R. Bertran, M. Floyd, M. Ware, G. Salem, S. Carey, P. Restle. Power Supply Noise in a 22nm z13 Microprocessor. International Solid-State Circuits Conference (ISSCC), February 2017.
  7. K. Swaminathan, N. Chandramoorthy, C. Cher, R. Bertran, A. Buyuktosunoglu, P. Bose. BRAVO: Balanced Reliability-Aware Voltage Optimization. International Symposium on High-Performance Computer Architecture (HPCA), February 2017.
  8. H. Sasaki, A. Buyuktosunoglu, A. Vega, P. Bose. Mitigating Power Contention: A Scheduling Based Approach. IEEE Computer Architecture Letters, Vol. 16, January-June 2017.
  9. A. Vega, P. Bose, A. Buyuktosunoglu. Rugged Embedded Systems: Computing in Harsh Environments, November 2016. ISBN: 978-0128024591 (book from Morgan Kaufmann).
  10. H. Sasaki, A. Buyuktosunoglu, A. Vega, P. Bose. Characterization and Mitigation of Power Contention across Multiprogrammed Workloads, International Symposium on Workload Characterization (IISWC), September 2016.
  11. R. Venkatagiri, K. Swaminathan, C. Lin, L. Wang, A. Buyuktosunoglu, P. Bose, S. Adve. Resilience Characterization of a Vision Analytics Application Under Varying Degrees of Approximation, International Symposium on Workload Characterization (IISWC), September 2016.
  12. W. Song, A. Buyuktosunoglu, C. Cher, P. Bose, Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency, International Symposium on Low-Power Electronics and Design (ISLPED), August 2016.
  13. P. Parida, A. Vega, A. Buyuktosunoglu, P. Bose, T. Chainer. Embedded Two Phase Liquid Cooling for Increasing Computational Efficiency. The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), May 2016.
  14. J. Leng, A. Buyuktosunoglu, R. Bertran, P. Bose, V. Reddi. Safe Limits on Voltage Reduction Efficiency in GPUs: a Direct Measurement Approach.  International Symposium on Microarchitecture (MICRO), December 2015.
  15. A. Vega, C. Lin, K. Swaminathan, A. Buyuktosunoglu, S. Pankanti, P. Bose. Resilient, UAV-Embedded Real-Time Computing. Special Session on Reliable and Secure Mobile Cognition. International Conference on Computer Design (ICCD), October 2015.
  16. R. Viguier, C. Lin, K. Swaminathan, A. Vega, A. Buyuktosunoglu, S. Pankanti, P. Bose, H. Akbarpour, F. Bunyak, K. Palaniappan, G. Seetharaman. Resilient Mobile Cognition: Algorithms, Innovations, and Architectures. Special Session on Reliable and Secure Mobile Cognition. International Conference on Computer Design (ICCD), October 2015.
  17. T. Webel, P. Lobo, R. Bertran, G. Salem, M. Ware, R. Rizzolo, S. Carey, T. Strach, A. Buyuktosunoglu, C. Lefurgy, P. Bose, R. Nigaglioni, T. Slegel, M. Floyd, B. Curran. Robust Power Management in the IBM z13. IBM Journal of Research and Development, Vol. 59, July/September 2015.
  18. L. Wang, A. Vega, A. Buyuktosunoglu, K. Skadron, P. Bose. Power-Efficient Embedded Processing with Resilience and Real-Time Constraints. International Symposium on Low Power Electronics and Design (ISLPED), July  2015.
  19. K. Swaminathan, C. Lin, A. Vega, A. Buyuktosunoglu, P. Bose, S. Pankanti. A Case for Approximate Computing in Real-Time Mobile Cognition. Workshop on Approximate Computing (WACAS), in conjunction with ASPLOS, March 2015.
  20. V. Jimenez, A. Buyuktosunoglu, P. Bose, F. O'Connell, F. Cazorla, M. Valero. Increasing Multicore System Efficiency through Intelligent Bandwidth Shifting. International Symposium on High- Performance Computer Architecture (HPCA), February 2015.
  21. R. Bertran, A. Buyuktosunoglu, P. Bose, T. Slegel, G. Salem, S. Carey, R. Rizzolo, T. Strach. Voltage Noise in Multi-core Processors: Empirical Characterization and Optimization Opportunities. International Symposium on Microarchitecture (MICRO), December 2014.
  22. A. Vega, A. Buyuktosunoglu, P. Bose. Harsh Chips. Guest Editors' Introduction for Special Series on Harsh Chips, IEEE Micro, November/December 2014.
  23. L. Wang, R. Bertran, M. Gupta, A. Buyuktosunoglu, P. Bose, K. Skadron. Characterization of Transient Error Tolerance for a Class of Mobile Embedded Applications. International Symposium on Workload Characterization (IISWC), October 2014.
  24. H. Jacobson, A. Joseph, D. Parikh, P. Bose, A. Buyuktosunoglu. Empirically Derived Abstractions in Uncore Power Modeling for a Server-Class Processor Chip. International Symposium on Low Power Electronics and Design (ISLPED), August 2014.
  25. S. Pugsley, J. Jestes, R. Balasubramonian, V. Srinivasan, A. Buyuktosunoglu, A. Davis, F. Li. Comparing Different Implementations of Near Data Computing with In-Memory MapReduce Workloads. IEEE Micro, July/August 2014.
  26. V. Jimenez, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, P. Bose, F. O'Connell, B. Mealey. Adaptive Prefetching on POWER7: Improving Performance and Power Consumption. ACM Transactions on Parallel Computing, Vol. 1, May 2014.
  27. L. Wang, P. Bose, J. Rivers, M. Gupta, A. Vega, A. Buyuktosunoglu, K. Skadron. Resilience and Real-Time Constrained Energy Optimization in Embedded Processor Systems. Workshop on Silicon Errors in Logic-System Effects (SELSE), April 2014.
  28. S.Pugsley, J. Jestes, H. Zhang, R. Balasubramonian, V. Srinivasan, A. Buyuktosunoglu, A. Davis, F. Li. NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads. International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014.
  29. P. Emma, A. Buyuktosunoglu, M. Healy, K. Kailas, V. Puente, R. Yu, A. Hartstein, P. Bose, J. Moreno. 3D Stacking of High-Performance Processors. International Symposium on High-Performance Computer Architecture (HPCA), February 2014.
  30. A. Vega, A. Buyuktosunoglu, H. Hanson, P. Bose, S. Ramani. Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control. International Symposium on Microarchitecture (MICRO), December 2013.
  31. P. Tembey, A. Vega, A. Buyuktosunoglu, D. Silva, P. Bose. SMT switch: Software Mechanisms for Power Shifting. IEEE Computer Architecture Letters, Vol. 12, July-Dec 2013.
  32. A. Vega, A. Buyuktosunoglu, P. Bose. SMT-Centric Power-Aware Thread Placement in Chip Multiprocessors. Best Paper Award Nominee. International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2013.
  33. A. Morari, C. Boneti, F. Cazorla, R. Gioiosa, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero. SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Transactions on Computers, Vol. 62, April 2013.
  34. R. Sarikaya, C. Isci, A. Buyuktosunoglu. Runtime Application Behavior Prediction Using a Statistical Metric Model. IEEE Transactions on Computers, Vol. 62, March 2013.
  35. R. Bertran, Y. Sugawara, H. Jacobson, A. Buyuktosunoglu, P. Bose. Application Level Power and Performance Characterization and Optimization on IBM BlueGene/Q Systems. IBM Journal of Research and Development, Vol. 57, January/February 2013.
  36. W. Huang, C. Lefurgy, W. Kuk, A. Buyuktosunoglu, M. Floyd, K. Rajamani, M. Ware, B. Brock. Accurate Fine-Grained Processor Power Proxies. International Symposium on Microarchitecture (MICRO), December 2012.
  37. R. Bertran, A. Buyuktosunoglu, M. Gupta, M. Gonzalez, P. Bose. Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks. International Symposium on Microarchitecture (MICRO), December 2012.
  38. V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, A. Buyuktosunoglu, P. Bose, F. O'Connell. Making Data Prefetch Smarter: Adaptive Prefetching on POWER7. Best Paper Award Nominee. International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2012.
  39. T. Wenisch, A. Buyuktosunoglu. Energy-Aware Computing. Guest Editors' Introduction for Special Issue on Energy-Aware Computing, IEEE Micro, September/October 2012.
  40. A. Vega, P. Bose, A. Buyuktosunoglu. Power-Aware Thread Placement in SMT/CMP Architectures. Workshop on Energy Efficient Design (WEED), in conjunction with ISCA, June 2012.
  41. P. Bose, A. Buyuktosunoglu, J. Darringer, M. Gupta, M. Healy, H. Jacobson, I. Nair, J. Rivers, J. Shin, A. Vega, A. Weger. Power Management of Multi-Core Chips: Challenges and Pitfalls. Invited Paper. Design, Automation & Test in Europe (DATE), March 2012.
  42. C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. CPU Accounting for Multicore Processors. IEEE Transactions on Computers, Vol. 61, February 2012.
  43. A. Vega, P. Bose, A. Buyuktosunoglu, J. Derby, M. Franceschini, C. Johnson, R. Montoye. Architectural Perspectives of Future Wireless Base Stations based on the IBM PowerEN Processor. International Symposium on High-Performance Computer Architecture (HPCA), February 2012.
  44. V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Cher, C. Isci, A. Buyuktosunoglu, P. Bose. Characterizing Power and Temperature Behavior of POWER6-Based System. Invited Paper. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 1, September 2011.
  45. V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose. Energy Aware Accounting and Billing in Large Scale Computing Facilities. IEEE Micro, May/June 2011.
  46. M. Floyd, M. Ware, K. Rajamani, T. Gloekler, B. Brock, P. Bose, A. Buyuktosunoglu, J. Rubio, B. Schubert, B. Spruth, J. Tierno, L. Pesantez. Adaptive Energy Management Features of the IBM POWER7 Chip. IBM Journal of Research and Development, Vol. 55, May/June 2011.
  47. M. Floyd, M. Ware, K. Rajamani, B. Brock, C. Lefurgy, A. Drake, L. Pesantez, T. Gloekler, J. Tierno, P. Bose, A. Buyuktosunoglu. Introducing the Adaptive Energy Management Features of the POWER7 chip. IEEE Micro, March/April 2011.
  48. H. Jacobson, A. Buyuktosunoglu, P. Bose, E. Acar, R. Eickemeyer. Abstraction and Microarchitecture Scaling in Early-Stage Power Modeling. International Symposium on High-Performance Computer Architecture (HPCA), February 2011.
  49. N. Madan, A. Buyuktosunoglu, P. Bose, M. Annavaram. A Case for Guarded Power Gating for Multi-Core Processors. International Symposium on High-Performance Computer Architecture (HPCA), February 2011.
  50. R. Sarikaya, C. Isci, A. Buyuktosunoglu. Runtime Workload Behavior Prediction Using Statistical Metric Modeling with Application to Dynamic Power Management. International Symposium on Workload Characterization (IISWC), December 2010.
  51. V. Jimenez, R. Gioiosa, E. Kursun, F. Cazorla, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero. Trends and Techniques for Energy Efficient Architectures. Invited Paper. International Conference on VLSI and System-on-Chip (VLSI-SoC), September 2010.
  52. V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero. Power and Thermal Characterization of POWER6 System. International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2010.
  53. V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose, M. Valero. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, June 2010.
  54. N. Madan, A. Buyuktosunoglu, P. Bose, M. Annavaram. Guarded Power Gating in a Multi-Core Setting. Workshop on Energy Efficient Design (WEED), in conjunction with ISCA, June 2010.
  55. K. Kedzierski, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, June 2010.
  56. R. Sarikaya, C. Isci, A. Buyuktosunoglu. Program Behavior Prediction Using a Statistical Metric Model. ACM SIGMETRICS, June 2010.
  57. P. Bose, A. Buyuktosunoglu, C. Cher, J. Darringer, M. Gupta, H. Hamann, H. Jacobson, P. Kudva, E. Kursun, N. Madan, I. Nair, J. Rivers, J. Shin, A. Weger, V. Zyuban. Power-efficient, Reliable Microprocessor Architectures: Modeling and Design Methods. Invited Paper. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
  58. R. Sarikaya, A. Buyuktosunoglu. A Unified Prediction Method for Predicting Program Behavior. IEEE Transactions on Computers, Vol 59, No 2, February 2010.
  59. C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2009.
  60. A. Lungu, P. Bose, A. Buyuktosunoglu, D. Sorin. Dynamic Power Gating with Quality Guarantees. International Symposium on Low Power Electronics and Design (ISLPED), August 2009.
  61. C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. CPU Accounting in CMP Processors. IEEE Computer Architecture Letters, vol. 8, April 2009.
  62. C. Boneti, F. Cazorla, R. Gioiosa, M. Valero, A. Buyuktosunoglu, C. Cher. Software-Controlled Priority Characterization of POWER5 Processor. International Symposium on Computer Architecture (ISCA), June 2008.
  63. R. Bergamaschi, G. Han, A. Buyuktosunoglu, H. Patel, I. Nair, G. Janssen, G. Dittman, N. Dhanwada, Z. Hu, P. Bose, J. Darringer. Exploring Power Management in Multi-Core Systems. Asia and South Pacific Design Automation Conference (ASP-DAC), January 2008.
  64. R. Bergamaschi, I. Nair, G. Dittmann, H. Patel, G. Janssen, N. Dhanwada, A. Buyuktosunoglu, E. Acar, G. Nam, G. Han, D. Kucar, P. Bose, J. Darringer. Performance Modeling for Early Analysis of Multi-core Systems. Invited Paper. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2007.
  65. R. Sarikaya, A. Buyuktosunoglu. Predicting Program Behavior Based on Objective Function Minimization. International Symposium on Workload Characterization (IISWC), September 2007.
  66. J. Sharkey, A. Buyuktosunoglu, P. Bose. Evaluating Design Tradeoffs in On-Chip Power Management for CMPs. International Symposium on Low Power Electronics and Design (ISLPED), August 2007.
  67. C. Isci, A. Buyuktosunoglu, C. Cher, P. Bose, M. Martonosi. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. 39th International Symposium on Microarchitecture (MICRO), December 2006.
  68. E. Kursun, C. Cher, A. Buyuktosunoglu, P. Bose. Investigating the Effects of Task Scheduling on Thermal Behavior. Workshop on Temperature-Aware Computer Systems (TACS), in conjunction with ISCA, June 2006.
  69. C. Isci, M. Martonosi, A. Buyuktosunoglu. Long-Term Workload Phases: Duration Predictions and Applications to DVFS. IEEE Micro, September/October 2005.
  70. Y. Zhu, D. H. Albonesi, A. Buyuktosunoglu. A High Performance, Energy Efficient GALS Processor Microarchitecture with Reduced Implementation Complexity. International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2005.
  71. H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R. Eickemeyer, L. Eisen, J. Griswell, D. Logan, B. Sinharoy, J. Tendler. Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. High-Performance Computer Architecture (HPCA), February 2005.
  72. R. Balasubramonian, V. Srinivasan, S. Dwarkadas, A. Buyuktosunoglu. Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. Springer-Verlag Lecture Notes in Computer Science Volume 3164, December 2004.
  73. Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, P. Bose, H. Jacobson. Microarchitectural Techniques for Power Gating of Execution Units. International Symposium on Low Power Electronics and Design (ISLPED), August 2004.
  74. D. H. Albonesi, R. Balasubramonian, S. Dropsho, S. Dwarkadas, E. G. Friedman, M. Huang, V. Kursun, G. Magklis, M. L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P. W. Cook, S. E. Schuster. Adaptive Processing: Dynamically Tuning Processor Resources for Energy Efficiency. IEEE Computer, December 2003.
  75. R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. A Dynamically Tunable Memory Hierarchy. IEEE Transactions on Computers, Vol 52, No 10, October 2003.
  76. A. Buyuktosunoglu, D. H. Albonesi, T. Karkhanis, P. Bose. Energy Efficient Co-Adaptive Instruction Fetch and Issue. 30th Annual International Symposium on Computer Architecture (ISCA), June 2003.
  77. P. Bose, D. Brooks, A. Buyuktosunoglu, P. W. Cook, K. Das, P. Emma, M. Gschwind, H. Jacobson, T. Karkhanis, P. Kudva, S. E. Schuster, J. Smith, V. Srinivasan, V. Zyuban, D. H. Albonesi, S. Dwarkadas. Early-Stage Definition of LPX : a Low Power Issue-Execute Processor. Power-Aware Computer Systems, Springer-Verlag Lecture Notes in Computer Science Volume 2325, May 2003.
  78. A. Buyuktosunoglu, D. H. Albonesi, S. E. Schuster, D. Brooks, P. Bose, P. W. Cook. Power-Efficient Issue Queue Design. Power Aware Computing, R. Graybill and R. Melhem (Eds), Kluwer Academic Publishers, Chapter 3, pp. 37-60, 2002.
  79. B. Curran, M. Gifaldi, J. Martin, A. Buyuktosunoglu, M. Margala, D. H. Albonesi. Low-Voltage 0.25um CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. SOC Design Methodologies, M. Robert, B. Rouzeyre, C. Piguet, and M. L. Flottes (Eds), Kluwer Academic Publishers, pp. 289-300, 2002.
  80. S. Dropsho, A. Buyuktosunoglu, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, G. Semeraro, G. Magklis, M. Scott. Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. 11th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2002.
  81. A. Buyuktosunoglu, A. El-Moursy, D. H. Albonesi. An Oldest-First Selection Logic Implementation for Non-Compacting Issue Queues. 15th Annual International ASIC/SOC Conference, September 2002.
  82. A. Buyuktosunoglu, D. H. Albonesi, P. Bose, P. W. Cook, S. E. Schuster. Tradeoffs in Power-Efficient Issue Queue Design. International Symposium on Low Power Electronics and Design (ISLPED), August 2002.
  83. A. Buyuktosunoglu, S. E. Schuster, D. Brooks, P. Bose, P. W. Cook, D. H. Albonesi. An Adaptive Issue Queue for Reduced Power at High Performance. Power Aware Computer Systems, Springer-Verlag Lecture Notes in Computer Science Volume 2008, May 2001.
  84. A. Buyuktosunoglu, S. E. Schuster, D. Brooks, P. Bose, P. W. Cook, D. H. Albonesi. A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors. 11th Great Lakes Symposium on VLSI (GLSVLSI), March 2001.
  85. R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. 33rd International Symposium on Microarchitecture (MICRO), December 2000.
  86. D. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J. Wellman, V. Zyuban, M. Gupta, P. W. Cook. Power Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro, November/December 2000.
  87. R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. Dynamic Memory Hierarchy Performance Optimization. Workshop on Solving the Memory Wall Problem, in conjunction with ISCA, June 2000.