In order to deliver increasing capacity and performance, VLSI chips are made from shrinking devices, with feature size going from 45nm to 32nm, 22nm and beyond. Devices and interconnects have become so small that imperfection during manufacturing can no longer be ignored, some examples illustrated in the figure below. Consequently, two chips with identical design but from two semiconductor fabs would have different performance, two chips from the same fab but on two wafers would be different, two chips on the same wafer would be different, and even two identical devices on the same chip would behave differently.

This demands fundamental changes in design and test:

1.      Timing analysis, which predicts circuit performance at design time, can no longer be deterministic. It must take statistical information about variation sources, and predict circuit performance as a statistical distribution.

2.      At-speed testing, which checks chips after manufacturing by applying a set of input patterns, can no longer be confident with patterns that check only a few timing paths on a chip, because virtually all timing paths have a possibility to fail at some point in the variation space. At-speed testing must take statistical information about a chip design, and select input patterns that provide the maximum confidence -- the likelihood of a faulty chip passing the tests is minimized.

3.      Circuit optimization at design time can no longer be based on deterministic information. Instead, circuit optimization should take statistical constraints and optimize the statistical performance of a design.

The Statistical Timing Analysis project is a framework of parameterized block-based statistical timing analysis. A first-order canonical form is used for representing delay time variations and gets propagated through circuit netlist efficiently. The end report includes metrics such as circuit delay distributions, chip yield, and sensitivities with respect to variation sources. The tool has been applied on multiple chip designs, and experimental results show not only good correlation with those of Monte-Carlo simulations, but also good correlation with silicon measurements.

The Statistical At-speed Test project builds on the foundation of statistical timing analysis, and optimally selects paths for detecting delay faults due to process variations. The approach is based on a new Test Quality Metric (TQM). Tight bounds on the TQM are developed and are leveraged in an efficient branch-and-bound path enumeration procedure. The tool has been used to generate test patterns for multiple chip designs, and, for chips with multi-million gates, the algorithm is able to select a thousand paths within a few seconds, while maximizing test coverage of variation space.