Project Name


DAISY: Dynamically Architected Instruction Set from Yorktown

Download DAISY code subject to IBM open source license.

The VLIW effort at the IBM T.J. Watson Research Center started in 1986 and has yielded several generations of compilers as well as prototype hardware. DAISY (Dynamically Architected Instruction Set from Yorktown) is an offshoot of this work, and aims to make VLIW and other novel ILP architectures 100% compatible with popular existing architectures such as PowerPC, x86, and S/390, as well as the Java Virtual Machine.

A variety of VLIW and other novel ILP architectures have been proposed over the years. VLIW offers the prospect of high issue rates and a significant advantage in simplicity over out-of-order superscalar implementations. However, lack of compatibility with existing architectures (as well as between generations of VLIW) has prevented its widespread adoption. To attack this compatibility problem, DAISY introduces simple hardware features intended to simplify emulation of existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes.

DAISY Architecture

DAISY Architecture DAISY works as follows. Each time a new fragment of code (such as a page) is executed for the first time, the code is translated to simple RISC-like primitives, parallelized and saved in a portion of main memory not visible to the old architecture. Subsequent executions of the same fragment do not require a translation (unless cast out). DAISY includes new fast compiler algorithms for accomplishing the dynamic translation and parallelization across multiple paths and loop iteration boundaries. A demonstration and tutorial of this algorithm may be viewed online, as can a detailed Research Report, DAISY: Dynamic Compilation for 100% Architectural Compatibility.

The Research Report also discusses the architectural requirements for a DAISY-like machine, be it VLIW or some other novel architecture. Other issues dealt with in the Report include self-modifying code, precise exceptions, and aggressive reordering of memory references in the presence of strong MP consistency and memory mapped I/O. Initial results are reported from a DAISY implementation mapping PowerPC to a VLIW architecture. Finally, the Report shows a method for approaching oracle parallelism levels in the same framework (trading off increased compilation overhead).

A companion to the Research Report is a paper, entitled A Java Processor Based on Fast Dynamic VLIW Compilation. This paper was presented at the International Workshop on Security and Efficiency Aspects of Java, which was held in conjunction with the 1997 IEEE MASCOTS Conference. Summary of useful DAISY links: