2011 Pat Goldberg Best Paper Award Selection Committee

Anupam Joshi

Phokion Kolaitis

Steve Lavenberg

Yue Pan

Dale Pearson

Claudio Pinhanez

Sara Porat

Baruch Schieber

Kohichi Takeda

Olivier Verscheure

Hagen Voelzer

Related links

IBM Research

Computer Science

Electrical Engineering

Mathematical Science

Project Name

Pat Goldberg Best Paper Awards for 2011 announced


Tab navigation

2011 Best Paper awards focus on barium ferrite tape, saving energy in POWER7, security protocols, algorithm optimization and wireless chipsets.

fractalMore than 110 papers in computer science, electrical engineering and mathematical sciences published in refereed conference proceedings and journals in 2011 were submitted by IBM Research authors worldwide for the 2011 Pat Goldberg Memorial Best Papers in CS, EE and Math.

As usual, the overall quality of the papers was high. From these submissions, the Research Professional Interest Communities (PICs) nominated 38 papers based on technical significance (depth and breadth) and expected impact on computer science, electrical engineering or mathematical sciences, or their applications in the research disciplines covered by the PICs.

A committee consisting of the PIC site coordinators (see sidebar) and head of IBM Computer Science Laura Haas reviewed the nominated papers and selected the following five as winners of the 2011 Pat Goldberg Memorial best paper awards:

Paper title: 29.5-Gb/in^2 Recording Areal Density on Barium Ferrite Tape (access full pdf)

Name of journal or conference: IEEE Transactions on Magnetics

Authors and affiliations: Giovanni Cherubini (1), Roy D. Cideciyan (1), Laurent Dellmann (1), Evangelos Eleftheriou (1), Walter Haeberle (1), Jens Jelitto (1), Venkataraman Kartik (1), Mark A. Lantz (1), Sedat Olcer (1), Angeliki Pantazi (1), Hugo E. Rothuizen (1), David Berman (2), Wayne Imaino (2), Pierre-Olivier Jubert (2), Gary McClelland (2), Peter V. Koeppe (3), Kazuhiro Tsuruta (4), Takeshi Harasawa (5), Yuto Murata (5), Atsushi Musha (5), Hitoshi Noguchi (5), Hiroki Ohtsu (5), Osamu Shimizu (5), and Ryota Suzuki (5)

(1) IBM Research-Zurich

(2) IBM Research-Almaden

(3) IBM Systems & Technology Group, San Jose

(4) IBM Systems & Technology Group, Yamato

(5) Recording Media Research Laboratories, FUJIFILM Corporation

Summary: This paper describes a magnetic tape recording demonstration performed in collaboration with FujiFilm at a world record areal density of 29.5 Gb/in2 -- about 39 times the density of fourth-generation Linear Tape-Open (LTO Gen4). This was achieved through the development of a set of new technologies that are described in the paper. Specifically, using a low lateral tape motion tape path, a new servo pattern, prototype perpendicularly oriented BaFe media, a new low friction head technology, a novel synchronous servo channel and advanced servo control concepts, a record closed-loop track-follow performance with a 23.4 nm standard deviation of position-error signal was demonstrated -- more than 20x better than in IBM LTO tape drives. This level of track-following fidelity allows a track pitch of 446nm, corresponding to a more than a 25-fold increase in track density. In addition, using read back waveforms captured on the same advanced perpendicularly oriented BaFe medium with a 0.2-micro-m-wide data reader, write/read performance at 518 kbpi using advanced noise-predictive maximum likelihood (NPML) detection schemes was demonstrated. Combining these results demonstrates an achievable areal density of 29.5 Gb/in2.

This achievement demonstrates IBM's tape technology leadership as well as the sustainability of the tape road map for at least the next 10 years. Several of the developed technologies are already in use in Jaguar 4 (IBM’s latest enterprise tape drive). And they have helped enable an acceleration from the traditional doubling of capacity with each new generation to the 4x increase achieved with Jaguar 4.

The work resulted in two keynote talks at two highly prestigious magnetic recording conferences: the Information Storage Industry Consortium (INSIC) Symposium and the Magnetic Recording Conference (TMRC).

Paper title: Active Management of Timing Guardband to Save Energy in POWER7 (summary)

Name of journal or conference: Proceedings of the 44th Annual International Symposium on Microarchitecture (MICRO-44)

Authors and affiliations: Charles R. Lefurgy (1), Alan J. Drake (1), Michael S. Floyd (2), Malcolm S. Allen-Ware (1), Bishop Brock (2), Jose A. Tierno (3), John B. Carter (1)

(1) IBM Research - Austin

(2) IBM Sytems & Technology Group, Austin

(3) IBM Research - Watson

Summary: The paper, which won the Best Paper Award at the MICRO conference (a PIC top quality conference), presents techniques to dynamically adjust microprocessor timing margins by reducing the voltage as much as possible to save power. The paper presents the implementation of the technique in a POWER7 system. The proposed method reduces the processor power by 24 percent on average without any performance loss.

The techniques proposed in the paper are not only academically important. They are also important for current and future IBM products. The technique shown in the paper will be a feature in POWER7+ systems to enable super turbo frequency on POWER7+.

In this particular area of research, researchers struggled to come up with a working implementation at a product level for many years. This paper for the first time does an end-to-end implementation that will be shipped with a product.

It also describes novel guardband reduction techniques and control mechanisms as well as a novel approach that prevents voltage droops using fast (relying on digital PLL) frequency adjustments.

Paper title: A Framework for Practical Universally Composable Zero-Knowledge Protocols (access full pdf)

Name of journal or conference: Asiacrypt 2011

Authors and affiliations: Jan Camenisch (IBM Research - Zurich), Stephan Krenn (University of Fribourg), Victor Shoup (New York University)

Summary: Zero-knowledge proofs of knowledge (ZK-PoK) are extremely powerful building blocks in the design of cryptographic protocols such as digital signatures, anonymous credentials, e-cash and electronic voting. This paper, which received the Best Paper Award at Asiacrypt 2011 (a PIC targeted conference), presents a generic language and compiler for discrete-logarithm-related statements that generate *efficient* ZK-PoK protocols that are secure in the universal composability (UC) framework. The latter is a very strong security notion that guarantees security even when protocols are composed in arbitrary ways. Previous such transformations generated protocols that are too inefficient for use in practical protocols.

UC security is often criticized for being "too strong for practice" in the sense that the added cryptographic machinery is prohibitive for practical use. This situation is somewhat reminiscent of the status of (non-UC) provable security in the early 'nineties, when theoretical constructions existed but were too inefficient for practice. The results of Camenisch et al. are in a rare class of efficient yet UC-secure protocols, essentially demonstrating that with careful design, UC security could make the step from mere theoretical feasibility results to actual usable schemes. Provable (non-UC) security is currently an important aspect that is taken into account in the selection of real-world industry standards. It is still unclear whether UC security will ever find a similar level of acceptance, but if it does, then it will be thanks to results like this one.

Paper title: Large-Scale Matrix Factorization with Distributed Stochastic Gradient Descent (summary)

Name of journal or conference: 17th ACM SIGKDD Conference on Knowledge Discovery and Data Mining (KDD '11)

Authors and affiliations: Rainer Gemulla (Max Planck Institute- Saarbrucken), Peter Haas (IBM Research - Almaden), Erik Nijkamp (IBM Research - Almaden), Yannis Sismanis (IBM Research - Almaden)

Summary: This paper was delivered at SIGKDD 2011 (a PIC top quality conference). It describes a novel approach to scaling up low-rank matrix-factorization (MF) algorithms to massive data. MF problems are fundamental to a variety of knowledge discovery tasks, such as keyword search, news personalization and recommendation systems. They have been used to solve a variety of client problems over the past few years.

Rather than simply implementing an embarrassingly parallel algorithm, as with prior work, the authors have taken an algorithm (stochastic gradient descent) known to have superior performance in sequential settings and parallelized it using a novel data stratification approach. It is hard to implement it in a distributed fashion due to the sequential dependence between consecutive updates.

The paper noted a key insight, the interchangeability of instances for stochastic gradient descent (SGD) when dealing with matrix factorization models. This leads to the first fully distributed (in both data and model parameters) and "generic" (w.r.t. loss function) matrix factorization algorithm.

An abbreviated version of this paper subsequently won the Best Paper Award at the 2011 NIPS Big Learning Workshop. The authors were invited to talk about their results at EBay and to Michael Jordan's group at UC Berkeley, received requests for the code from the Netezza development team and contributed the code to a client engagement with Bank of China. The approach taken by the authors will likely influence other efforts in the parallel ML area.

Paper title: Organic Packages with Embedded Phased-Array Antennas for 60-GHz Wireless Chipsets (access full pdf)

Name of journal or conference: IEEE Transactions on Components, Packaging and Manufacturing Technology

Authors and affiliations: Dong Gun Kam, Duixian Liu, Arun Natarajan, Scott Reynolds, Brian Floyd (IBM Research - Watson)

Summary: The 60-GHz band supports multi-Gb/s wireless communication, leveraging the large amount of available and unlicensed bandwidth and attracting potential large-volume applications such as uncompressed high-definition video streaming and wireless docking stations for laptops. For the 60-GHz market to flourish, both low-cost semiconductor and low-cost antenna and packaging solutions are required.

The main contribution of this paper is that it showcases the first hardware demonstration of a low-cost 60-GHz antenna-in-package solution that uses standard organic printed circuit board processes and flip-chip technology.

The package includes sixteen phased-array antennas, an open cavity for housing the flip-chip attached RF chip and interconnects operating at DC–66 GHz. The packaged transmitter and receiver chipsets have demonstrated beam-steered, non-line-of sight links with data rates up to 5.3 Gb/s.

While the end result, a low-cost antenna-in-package (AiP) solution, is the primary object of the paper, the design and simulation techniques underlying this design -- and their integration to produce the end result -- represent a truly outstanding engineering accomplishment.

Last updated on September 10, 2012