In order to deliver increasing capacity and performance, VLSI chips are made from shrinking devices, with feature size going from 45nm to 32nm, 22nm and beyond. At the same time, wavelength of light used in photolithography, a key step in making these devices, remains 193nm for the foreseeable future. This implies making shapes with dimensions that are a small fraction of the lithography light wavelength, and is a daunting task that challenges limits of physics. The above is just one of reasons that the cost to build up a semiconductor fab for a new technology generation is increasing, and into billions of dollars.

In the initial stages of technology development, numerous lithography and other process parameters are fine tuned to improve printability and manufacturing variations. However, electrical quality of the layout is often ignored, mainly due to the lack of an integrated tool which accurately estimates the electrical impact of lithography and process tuning. The following pictures illustrate two of the leading sources of process variation that impact layout quality.

1.      The first picture shows intended ideal device shapes versus actual shapes made through photolithography. Note that the actual shapes also depend on where the device is located on the silicon wafer. Such variability in shapes causes variability in electrical properties of the device, e.g., delay.

2.      The second picture shows uncertainty in doping process. Devices have become so small that there may be only dozens of dopants in one device, and therefore the randomness in the actual number of injected dopants can have a significant impact on electrical properties of the device, in particular, statistical fluctuation in threshold voltage.

The lack of integrated analysis tool results in many hardware verification cycles, which are expensive and time-consuming, during technology ramp-up. There is an immediate need for such an integrated tool because of escalating manufacturing variability and fabrication costs in 32nm and beyond.

The Virtual Fab project is a computational framework which integrates the lithography simulation tools and electrical yield analysis tools. The architecture is illustrated in the following picture; further details can be found in [1]. SRAM arrays are chosen as a first application, -- SRAM devices are the most aggressive in each technology generation and typically the first to fail under process variations. This integrated framework has been extensively verified with hardware and successfully used to analyze and optimize SRAM bit-cells in 45/32/22 nm generations. Using this framework, engineers at both ends of system development -- process/technology and circuit/system -- will be able to accurately estimate the lithography-aware electrical yield/performance of an SRAM array and other process sensitive designs. In particular, our methodology can be used to

1.      Determine the sensitivity of circuit/system level electrical parameters to lithography parameters;

2.      Evaluate the impact of process fine tuning on SRAM array electrical yield and performance;

3.      Do lithography-aware SRAM cell/peripheral circuit optimization.

 

 

Publications

[1]            A. Bansal, R. N. Singh, R. N. Kanj, S. Mukhopadhyay, J. Lee, E. Acar, A. Singhee, K. Kim, C. Chuang, S. Nassif, F. Heng and K. K. Das, Yield estimation of SRAM circuits using Virtual SRAM Fab, Proceedings of the 2009 International Conference on Computer-Aided Design, pp. 631-636, 2009.

[2]            F.-L. Heng, J.-F. Lee and P. Gupta, Toward through-process layout quality metrics, Proceedings of SPIE, pp. 161-167, 2005.