The VLIW protoype has a pipelined design, consisting of three stages:

1. compute next instruction address from condition codes, fetch next instruction;
2. register file access or bypass, ALU operation; and
3. write back ALU result to the register file.

The prototype cycle time is 90 ns; it was built using 5 Volt Schottky (FAST) TTL MSI parts, PALs, off the shelf 32-bit ALUs and multipliers, static RAM, and multiple copies of an IBM CMOS IIs semicustom chip that implements three different functions (depending on a "chip characteristic" input):

1. a 24-port register file capable of performing 16 read and 8 write operations in a single cycle (to support the 8 ALUs);
2. a next address multiplexer for 8-way branching and conditional execution; and
3. a crossbar switch for performing 4 memory accesses from 8 interleaved memory banks.

The prototype is built from two boards (connected through a bridge card):

• The processor board, containing the register file chips, ALUs, crossbar switch chips and data memory.
• The instruction fetch board, containing the next address multiplexer chips, the instruction memory, and the clock generator.

Connections to a PS/2 card from both boards allow a PS/2 computer to load programs into the VLIW memory, perform I/O requests, start/stop/single-step its clock, read the LSSD scan chains and/or insert new values in the scan chains.

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Additional information:

• Discussion of the critical paths