3D Chip interconnection
We research 3D chip interconnection for performance gain and power reduction, because conventional CMOS scaling come closer to physical limit.
- Increase of device count per unit area and downsizing of device can be realized by stacking Si chips vertically, which were placed side by side conventionally.
- Wiring length can be cut down and power consumption can be reduced by replacing wirebond (mm order length) with through silicon via (TSV) and microbump (micron order length).
- Integration of mixed devices such as analog, digital, memory, CPU, and MEMS can be realized.
- TSV process for narrow pitch and low capacitance
- Low cost, high yield, high reliability of 3D chip interconnection
- Cooling technology for 3D stacked devices
Approaches in IBM Research-Tokyo：
- Micro connection pitch 150μm ⇒ 40μm ⇒ 10μm
- New die stacking process technique
- Ultra narrow gap resin fill technique
- Thermal management