David H. Allen, Sang H. Dhong, et al.
IBM J. Res. Dev
This embedded-DRAM macro is designed as a DRAM cache for a future gigahertz microprocessor system based on a logic-based DRAM technology. The most notable feature of this macro is its ability to run synchronously with a gigahertz CPU clock in a fully pipelined fashion. It is designed to operate with a 1-GHz clock signal at 85°C, nominal process parameters, and a 10% degraded VDD. The design is fully pipelined and synchronous with 16 independent subarrays. With 1-kb wide I/O and a 1-GHz clock, the maximum data rate becomes 1 Tb per second. The address access time is 3.7 ns, four cycles with a 1-GHz clock. The subarray cycle time is 12 ns.
David H. Allen, Sang H. Dhong, et al.
IBM J. Res. Dev
H. Peter Hofstee, Sang H. Dhong, et al.
IEEE Micro
Toshiaki Kirihata, Sang H. Dhong, et al.
IEEE Journal of Solid-State Circuits
Sang H. Dhong, Nicky Chau-Chun Lu, et al.
IEEE Journal of Solid-State Circuits