Zeynep Toprak-Deniz, Timothy O. Dickson, et al.
VLSI Technology and Circuits 2024
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER < 10-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally. © 2007 IEEE.
Zeynep Toprak-Deniz, Timothy O. Dickson, et al.
VLSI Technology and Circuits 2024
Kevin Tien, Ken Inoue, et al.
DATE 2022
John F. Bulzacchelli, Christian Menolfi, et al.
IEEE JSSC
Gautam R. Gangasani, Chun-Ming Hsu, et al.
CICC 2011