Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The parallel-plate formula is widely used by the solid-state circuit designer to estimate capacitances in integrated circuits. Since considerable errors may result from using this approximation, this correspondence gives correction curves for a wide range of parameters. It is shown that the finite conductor thickness may significantly contribute to the increase in capacitance. Copyright 1973 by The Institute of Electrical and Electronics Engineers, Inc.
Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE TCAS-I
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