Yao Qi, Raja Das, et al.
ISSTA 2009
This paper describes the design, fabrication, and characterization of 0.1-μm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-angstrom gate oxide. A 2× performance gain over 2.5-V, 0.25-μm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20× reduction in active power per circuit is obtained at a supply voltage < 1 V with the same delay as the 0.25-μm CMOS. These results demonstrate the feasibility of high-performance and low-power room-temperature 0.1-μm CMOS technology. Beyond 0.1 μm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed.
Yao Qi, Raja Das, et al.
ISSTA 2009
John M. Boyer, Charles F. Wiecha
DocEng 2009
Yun Mao, Hani Jamjoom, et al.
CoNEXT 2006
Liqun Chen, Matthias Enzmann, et al.
FC 2005