Marcel Kossel, Thomas Toifl, et al.
IEEE JSSC
Paper
Design methodology for a large communication chip
Abstract
Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.
Related
Ulf Schlichtmann, Veit B. Kleeberger, et al.
DATE 2014
Rolf Clauberg, Armin Blacha
Journal of Applied Physics
John F. Bulzacchelli, Christian Menolfi, et al.
IEEE JSSC