Conference paper
Nanowire FET design for 7-nm SOI-CMOS technology
Ishita Jain, Anil K. Bansal, et al.
S3S 2015
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Ishita Jain, Anil K. Bansal, et al.
S3S 2015
Ning Lu, Roger Booth, et al.
NSTI-Nanotech 2011
Ning Lu
ISQED 2008
Ning Lu, Richard A. Wachnik
IEEE TCAS-I