Ping-Lin Yang, Terence B. Hook, et al.
IEEE T-ED
We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET. © 1980-2012 IEEE.
Ping-Lin Yang, Terence B. Hook, et al.
IEEE T-ED
Ishita Jain, Anil K. Bansal, et al.
S3S 2015
Anil K. Bansal, Ishita Jain, et al.
IEEE J-EDS
R. Singh, K. Aditya, et al.
IEEE Electron Device Letters