Conference paper
VLIW - A case study of parallelism verification
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DAC 2005
Genesys-Pro is currently the main test generation tool for functional verification of IBM processors, including several complex processors. Although it requires a high level of expertise to model architectures and testing knowledge to use the full power of test templates, Genesys-Pro's benefits are already apparent. It is found that the new language considerably reduces the effort needed to define and maintain knowledge specific to an implementation and verification plan.
Allon Adir, Yaron Arbetman, et al.
DAC 2005
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DATE 1999
Eyal Bin, Laurent Fournier
MTV 2004
Allon Adir, Hezi Azatchi, et al.
DAC 2005