Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Paper
Observable time windows: Verifying high-level synthesis results
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.