B. Wagle
EJOR
A general theory for characterizing and then realizing algorithms in hardware is given. The physical process of computation is interpreted in terms of a graph in physical space and time, and then an embedding into this graph of another graph which characterizes data flow in particular algorithms is given. The types of the special class of computational structures called systolic arrays which can occur physically are completely described, and a technique is developed for mapping the graph of a particular systolic algorithm into a physical array. Examples illustrate the methodology. © 1984 Springer-Verlag.
B. Wagle
EJOR
Anupam Gupta, Viswanath Nagarajan, et al.
Operations Research
M.F. Cowlishaw
IBM Systems Journal
Michael D. Moffitt
ICCAD 2009