Phillip J. Restle, Timothy G. McNamara, et al.
IEEE Journal of Solid-State Circuits
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs.
Phillip J. Restle, Timothy G. McNamara, et al.
IEEE Journal of Solid-State Circuits
Charles J. Alpert, Shrirang K. Karandikar, et al.
Proceedings of the IEEE
He Zhou, Jiang Hu, et al.
BHI 2016
He Zhou, Sunil P. Khatri, et al.
ASP-DAC 2020