Strained-Si Devices and Circuits for Low-Power Applications
Keunwoo Kim, Rajiv V. Joshi, et al.
ISLPED 2003
This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme. © 2009 IEEE.
Keunwoo Kim, Rajiv V. Joshi, et al.
ISLPED 2003
Jie Deng, Lan Wei, et al.
VLSI-TSA 2008
Keunwoo Kim, Jerry G. Fossum, et al.
International Journal of Electronics
Rajiv V. Joshi, Richard Q. Williams, et al.
ESSDERC/ESSCIRC 2004