Publications

18 results for Brian Greene

Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- - M. Cai
  - B. Greene
  - et al.
- 2008
- IEEE International SOI Conference 2008
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- - B. Yang
  - R. Takalkar
  - et al.
- 2008
- IEDM 2008
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- - S. Fang
  - S.S. Tan
  - et al.
- 2008
- ICSICT 2008
Recent progress and challenges in enabling embedded Si:C technology
- - B. Yang
  - Z. Ren
  - et al.
- 2008
- ECS Meeting 2008
(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering
- - B. Yang
  - A. Waite
  - et al.
- 2007
- IEDM 2007
Mechanism of solid phase crystallization of prepatterned nanoscale α-Si pillars
- - Hyun-Jin Cho
  - Brian J. Greene
  - et al.
- 2007
- Journal of Applied Physics
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- - Haizhou Yin
  - Z. Ren
  - et al.
- 2006
- VLSI Technology 2006
Design of high performance PFETs with strained Si channel and laser anneal
- - Z. Luo
  - Y.F. Chong
  - et al.
- 2005
- IEDM 2005