Carl Radens  Carl Radens photo         

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Research Staff Member
Albany NY, and Yorktown Heights NY


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More information:  LinkedIn Profile


Technical leader and innovator with expertise in the semiconductor microelectronics industry focused on the R&D of SRAM and DRAM memory used in computer chips, communication devices, high-performance CPU, Mobile, system-on-chip (SoC), entertainment processors, graphics processors, and ASICs, for foundry, Platform and custom applications.


* Researching memory technology for hybrid cloud, systems and AI hardware
* Defining next-generation embedded memory technology and alignment with system specifications
* Optimizing silicon technology and design to meet the power/performance/schedule and complexity objectives of future products


h-index = 44 overall, 9091 citations


> 370 issued US patents


publications include (see LinkedIn profile for list and citations):

  • A comparative analysis of EUV sheet and gate patterning for beyond 7nm gate all around stacked nanosheet FET’s
  • Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM
  • A 7nm CMOS Technology Platform for Mobile and High Performance Compute Application
  • A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM
  • "Super-Fast Physics-based Methodology for Accurate Memory Yield Prediction"
  • High Performance 14nm SOI FinFET CMOS Technology with 0.xn--0174m2-zze embedded DRAM and 15 Levels of Cu Metallization
  • Fully-depleted planar technologies and static RAM
  • A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements
  • Embedded memory considerations in SOI
  • A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
  • A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing
  • Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?
  • Characterization of across-device linewidth variation (ADLV) for 65-nm logic SRAM using CDSEM and linewidth roughness algorithms
  • Fluctuation limits & scaling opportunities for CMOS SRAM cells
  • High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
  • Technologies for scaling vertical transistor DRAM cells to 70 nm
  • Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
  • Leakage current and reliability evaluation of ultra-thin reoxidized nitride and comparison with silicon dioxides
  • A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond
  • A lithographically-friendly 6F2 DRAM cell
  • + more



Honors & Awards

  • Invention Achievement Award 100th Plateau
  • Outstanding Technical Achievement Award in Appreciation for 45 nm Bulk Technology Development
  • Outstanding Technical Achievement Award in Appreciation for P6 Worlds Fastest Processor
  • Corporate Technical Recognition Event (CTRE) 3X
  • Division Portfolio Awards for High-Value Patent (17X)
  • Master Inventor (multiple recognitions)
  • Lifetime Master Inventor