Nandhini Chandramoorthy           

My research interests lie in the design and modeling of reliability and power aware architectures, and design, architecture and performance modeling of accelerator-rich multi-core architectures for computer vision and machine learning applications. Previously, I worked on fabrication of a 14nm chip consisting of a Deep Neural Network accelerator with low Vmin SRAMs, enabling high accuracy and reliable operation at very low voltages. Currently, I work on the DARPA DSSoC project with enthusiastic collaborators, both within IBM and academia.