Praveen Joseph  Praveen Joseph photo         

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Strategic Patterning Research
Semiconductor Technology Research


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Praveen is an advanced patterning researcher within the Strategic Patterning Research organization at the IBM Semiconductor Technology Research division, involved in both lithography and etch process R&D solutions for the 5 nm technology node and beyond. In his primary role, Praveen develops EUV lithography processes for beyond – 5 nm transistor architectures such as gate-all-around (GAA) devices, and supports immersion lithography (193i) processes for mature transistor architectures such as FinFETs. In his additional role, Praveen develops etch processes for GAA devices and FinFETs, and has significant interest in the integration of advanced semiconductor processes and materials to enable performance improvement elements in state-of-the-art transistors.

Prior to joining IBM Research, Praveen was a graduate student at the University of Texas at Austin where he received his Ph.D. (2017) in Mechanical Engineering, under the guidance of Prof. S.V. Sreenivasan, developing nanoimprint lithography processes in the NASCENT Engineering Research Center.

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