Praveen Joseph  Praveen Joseph photo         

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AI Hardware Center
Thomas J. Watson Research Center, Yorktown Heights, NY, USA


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Praveen is currently a researcher in the Accelerator Platforms group located within the TJ Watson Research Center in Yorktown Heights, NY. His current work falls under IBM Research Division’s AI Hardware Center, and pertains to hardware emulation of digital AI/ML/DL accelerator cores using reconfigurable computing platforms.

Prior to starting at the AI Hardware Center, Praveen was an advanced patterning researcher within the Strategic Patterning Research organization at the IBM Semiconductor Technology Research division based in Albany, NY, and was involved in both lithography and etch process R&D solutions for the 5 nm technology node and beyond. In his primary role, Praveen developed EUV lithography processes for beyond – 5 nm transistor architectures such as gate-all-around (GAA) devices, and supported immersion lithography (193i) processes for mature transistor architectures such as FinFETs. In his additional role, Praveen developed etch processes for GAA devices and FinFETs, and has significant interest in the integration of advanced semiconductor processes and materials to enable performance improvement elements in state-of-the-art transistors.

Prior to joining IBM Research, Praveen was a graduate student at the University of Texas at Austin where he received his Ph.D. (2017) in Mechanical Engineering, under the guidance of Prof. S.V. Sreenivasan, developing nanoimprint lithography processes in the NASCENT Engineering Research Center.  He received his M.S. degree in Mechanical Engineering from North Carolina State University in 2012 and a B.S. degree in Mechanical Engineering from College of Engineering Guindy, Anna University, Chennai in 2009.