I'm a Research Staff Member with the Reliability and Power-Aware Microarchitectures group working to dramatically improve the hardware design process.
I strive to bring new languages, compiler techniques, and tried-and-tested software engineering paradigms to the world of hardware. This involves active development of the Chisel hardware construction language, FIRRTL circuit Intermediate Representation, FIRRTL compiler, and a push to develop the Chisel/FIRRTL Hardware Compiler Framework.
I am currently funded through the DARPA DSSoC project where I work to improve the System-on-Chip design process working with Luca Carloni and the SLD group at Columbia.
Some open source projects that have grown out of this work include:
- Chisel Library for building ESP-compliant Accelerators
- Chiffre: Fault Injection Instrumentation via Chisel/Firrtl
- A Dynamically Allocated Neural Network Accelerator (DANA) for the RISC-V Rocket microprocessor
- Rocket Custom Coprocessor (RoCC) Software Tools
- Open source tools for working with hardware description languages (HDLs)
- Reusable Chisel Snippets
- An Emacs major mode for editing Firrtl
I received my Ph.D in Computer Engineering from Boston University in 2016 where I developed a simultaneously multithreaded model of neural network computation using the neural network accelerator referenced above (DANA).