I'm a postdoctoral researcher with the Reliability and Power-Aware Microarchitectures group working on the DARPA PERFECT and DSSoC programs. My research interests encompass hardware/software co-design of accelerators with a focus on machine learning acceleration. I additionally investigate means of instrumenting hardware designs to emulate low voltage operation via fault-injection. These interests directly overlap with a commitment to open-source hardware development. I'm currently involved in the RISC-V ecosystem and believe in the power and utility of new approaches to hardware design, specifically, Chisel and FIRRTL.
Some open source projects include:
- Chiffre: Fault Injection Instrumentation via Chisel/Firrtl
- A Dynamically Allocated Neural Network Accelerator (DANA) for the RISC-V Rocket microprocessor
- Rocket Custom Coprocessor (RoCC) Software Tools
- Open source tools for working with hardware description languages (HDLs)
- Reusable Chisel Snippets
- An Emacs major mode for editing Firrtl
I received my Ph.D in Computer Engineering from Boston University in 2016 where I developed a simultaneously multithreaded model of neural network computation using the neural network accelerator referenced above (DANA).