David Frank received his B.S. from the California Institute of Technology, Pasadena, CA in 1977 and a Ph.D. in physics from Harvard University, Cambridge, MA in 1983. Since graduation he has been employed at the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he is a Research Staff Member. His studies have included non-equilibrium superconductivity, III-V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, analysis of CMOS scaling issues such as power consumption, discrete dopant effects and short-channel effects associated with high-k gate insulators, exploring various nanotechnologies, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low power circuit design. Dr. Frank is an IEEE Fellow and has served as chairman of the Si Nanoelectronics Workshop and as associate editor of IEEE Transactions on Nanotechnology. He has authored or co-authored over 100 technical publications and holds 11 U.S. Patents.