I work in a small team with a big task: we define electrical tests and analyze test data for characterizing the entire Front End Of Line (FEOL) process sequence in IBM's 10 nm node CMOS technology development program. In the 10 nm program, ring oscillators are the "yield vehicle," which means the single most important measure of success is how consistently we can make ring oscillators which operate within their spec windows for frequency and power. Through ring oscillator test data, I evaluate the health of the baseline process and the suitability of proposed process changes.
Defect monitor structures for opens and shorts are another major part of my work, because when ring oscillators do fail, we need to know why. I use electrical test data from defect monitors to help explain ring oscillator data, and I continue to seek ways to improve the links between the two, either through testing of additional existing structures or designs of new structures.
An additional project I'm tackling in the second half of 2017 is an assessment of the overall electrical variability of our 10 nm CMOS hardware, with a decomposition into within-die, die-to-die, wafer-to-wafer, and lot-to-lot components.
Before I joined IBM Research in Albany in 2016, I worked for IBM Microelectronics in East Fishkill, NY for nearly 20 years, on characterization of a broad range of circuit types (DRAM, SRAM, logic, analog, non-volatile memory) within CMOS development programs.
I have B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Virginia, where my research focused on fabricating and characterizing low temperature superconducting tunnel junctions for millimeter wave radio astronomy.