Professional AssociationsProfessional Associations: IEEE | IEEE Computer Society | IEEE Mid-Hudson Section | IEEE, Senior Member
more informationMore information: Symposium on Computer Arithmetic - Steering Committee - General Chair
Z Series Mainframe microprocessor architect for future systems responsible for microarchitec-
ture and supporting architecture of the core on a mainframe. I also worked on Power9 core design
to reduce critical timing paths in the logic. Previously, microprocessor Chief Engineer for the z900
released in 2000, responsible for the logic design and for integrating all microprocessor teams. Ad-
visor to all server group floating-point units for future processors and official IBM representative to
the IEEE 754 revision committee. Led the first S/390 processor design to implement 64 bit addressing
(2000) and lead the first S/390 FPU to incorporate IEEE 754 binary floating-point standard (1998).
Drove decimal floating-point definition into international standard (754-2008), and into IBM archi-
tectures(PowerPC and zSeries), and lead designer of the first hardware implementations, Power6 (2007)
and helped on z10(2008) and lead microarchitecture of core on z196(2010). Introduced vector pro-
cessing back onto the mainframe by developing the architecture and microarchitecture of the z13
in-core SIMD accelerator for Business Analytics in 2015.
I have authored over 200 issued US patents in computer arithmetic and computer architecture and
have filed more than that in other countries. I've been general and program chair of the top computer
arithmetic conference in the world representing both industry and academia. I've been associate
editor and guest editor of IEEE Transactions on Computer. I've been on the PhD committees
of individuals at Lehigh University and Binghamton University. I've been appointed IBM Master
Inventor and Member of IBM Academy of Technology. I am IBM's Subject Matter Expert (SME)
on Computer Processor development for our Intellectual Property law department.