I am a Research Staff Member in the Austin Research Lab. I received my Master's degree in Applied Mathematics from University of Minnesota, and my Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University.
Over the years I have worked on various projects, including VLSI circuit analysis, numerical inverse lithography, Design for Manufacturability in VLSI.
Currently I am working on SPRINT.
Here is a webpage about SPRINT at the home page of Professor Ben Hodges, my collaborator at University of Texas at Austin. Here is a YouTube link to visualize the simulation results of a sizeable river network in Central Texas.
1. Y. Liu, L.T. Pileggi and A.J. Strojwas, "Model order-reduction of RC(L) interconnect including variational analysis", Proc. of ACM/IEEE Design Automation Conference, pp 201 - 206, 1999.
2. F. Liu, C. Kashyap, and C.J. Alpert, "A delay metric based on the Weibull distribution", Proc. of IEEE/ACM International Conference on CAD, 2002.
3. F. Liu, "A general framework for spatial correlation modeling in VLSI design", Proc. of ACM/IEEE Design Automation Conference, 2007.
4. F. Liu and X.-K. Shi, "An efficient mask optimization method based on homotopy continuation technique", Proc. of Design Automation and Testing Europe, 2011.
5. F. Liu and B.R. Hodges, "Dynamic river network simulation at large scale", Proc. of ACM/IEEE Design Automation Conference, 2012.
6. B.R. Hodges and F. Liu, "Rivers and Electric Networks: Crossing Disciplines in Modeling and Simulation", Foundation and Trends in Electronic Design Automation, NOW Publishing, Jan. 2014.
Over the years, I have served on the Technical Program Committees as regular member or subcommittee chair of major conferences such as DAC, ICCAD, ASP-DAC and others. Currently I am on the Executive Committee of ICCAD, serving as the vice-program chair.
I am also an elected member on the Executive Committee of ACM SIGDA.