Pouya Hashemi           

Pouya Hashemi received his Ph.D. degree (with honor) in Department of Electrical Engineering and Computer Science at Massachusetts Institute of Technology (MIT) in September 2010 and his B.Sc. and M.Sc. degrees in electrical engineering, both with highest honors, from University of Tehran in 2003 and 2005, respectively. 

He is currently a manager, research staff member, and master inventor at IBM research center at Yorktown Heights, NY, leading the Spin-Transfer-Torque MRAM Integration and Process team and running joint development projects with IBM partner companies. Since joining IBM, he has had hands on exploratory logic devices (high mobility strained SiGe, Ge, III-V PDSOI/FDSOI/FinFETs/GAA FETs), unconventional high-speed transistors (such as lateral bipolar) as well as memory devices (STT-MRAM) for advanced technology nodes. In 2010 and 2011, he was a post-doctoral associate at the MIT MTL working on advanced strained-Ge on insulator substrates and top-down fabricated Si/Ge nanowires for high-performance CMOS and SiGe based solar cells. From 2002 to 2005, he was with the Thin-Film Research Laboratories at University of Tehran working on electrical and optical properties of nano-crystalline silicon and fabrication of low temperature Si and Ge thin-film transistors on flexible substrates. In 2005, he joined MIT Microsystems Technology Laboratories where his research was focused on fabrication and investigation of carrier transport in nano-scale strained SOI, SiGe and Ge channel CMOS devices with planar and nanowire architectures. In summer 2009, he was with IBM research and worked on process development of multi-crystalline based Si solar cells.

He is the recipient of the 2014 IEEE George E. Smith award in 2015, IBM Ph.D. Fellowship award in 2008, TSMC outstanding research award/commendation in 2010, the Jin-Au Kong Award (Honorable Mention) for best MIT Electrical Engineering Ph.D. Thesis in 2011, and winner of the MIT Microsystems Technology Laboratories Doctoral Dissertation Seminar in Spring 2011.

His leading-edge research has led to over 100 peer-reviewed journals and conferences, including various invited talks in prestigious conferences such IEDM and VLSI Technology Symp. Pioneered the development of the "strained SiGe FinFETs for advanced logic technologies", his various advancement on this field have been presented at the highlight sessions or reflected on the tip-sheets at the VLSI and IEDM between 2013 and 2017. In addition, he has given CMOS Technology Short Course on 5nm node at the VLSI Technology Symp. in 2017, with over 1000 participants. Dr. Hashemi has contributed to over 550 issued US patents, holding the master inventor title at IBM since 2015. He is also a senior member of IEEE Electron Device Society and a committee member of ECS SiGe symposium.