Kyu-hyoun (Kh) Kim  Kyu-hyoun (Kh) Kim photo         

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Principal RSM & Technical Lead - DRAM and Future Memory
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash2216

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Professional Associations

Professional Associations:  IEEE Solid State Circuits Society  |  JEDEC  |  Korean-American Scientiests and Engineers Association

profile


Kyu-hyoun (KH) Kim received Ph.D. degree in Electrical and Electronic engineering from Korea Advanced Institute of Science and Technology (KAIST) in 1997. In 1998, he joined Samsung Electronics where he was involved in circuit design, product development and standardization of the high-performance dynamic RAMs such as DDR, DDR2, DDR3, Graphic memory and next-generation main memory. He was a leader of high-speed I/O circuit design and evaluation group for the development of commercial DRAM products. In 2005 and 2006, he was in charge of analog circuit development for high-resolution and high-speed CMOS image sensors. In July 2006, he joined IBM T. J.Watson Research Center, Yorktown Heights, NY, as a research staff member.

He has been in charge of memory subsystem research and development for IBM Data Centric Systems including BlueGene/Q, Exascale systems and AI machines. He has been also involved in development of high-speed I/O interface circuits for IBM servers.

He represents IBM in JEDEC Solid State Technology Association for standardization of memory components and modules. He received JEDEC Technical Recognition Award in 2011, in recognition of his 'outstanding contributions in the development of the DDR4 standard'.

He received 4 Outstanding Technical Achievement Awards in 2011, 2012, 2014 and 2016. In 2015, he became a Technical Lead for DRAM and Future Memory. In 2016, he was titled as Principal Research Staff Member.

Dr. Kim has presented eight papers to the International Solid-State Circuits Conference (ISSCC) as first authors between 1996 and 2009, and received ISSCC Takuo Sugano Outstanding Paper Award in 2007. He is a member of ISSCC ITPC Memory subcommittee since 2018.

He is holding 160 issued U.S. patents. He was elected IBM Master Inventor twice for 2011-2014, and 2015-2018.