Patrick J (Pat) Meaney  Patrick J (Pat) Meaney photo         

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Senior Technical Staff Member - IBM Z Memory & RAS, Master Inventor, Academy of Technology Member
Poughkeepsie, NY
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IBM Z Nest Interconnections/DLL, Chief Architect (2019-present)
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Provide for low latency, high bandwidth, reliable interconnects for IBM Z mainframes.
- Experience in High Speed SER/DES (serial/deserializer) technologies and their enablement for enterprise systems.

IBM Z Memory, Chief Architect (2008-present)
- Provide most available RAIM DRAM memory for our IBM Z Enterprise servers.
   (RAIM - Redundant Array of Independent Memory)
- Provide high RAS solutions for L3 and L4 levels of Processor Cache.
- IBM Z G4, G5, G6, z900, z990, z9, z10, z196, z114, zEC12, zBC12, z13, z13s, z14, zeus, and z15 CMOS systems
- DDR, DDR2, DDR3, DDR4 SDRAM
- Buffered DIMMs

Master Inventor - Since 2005

Academy of Technology - Member since 2020

Distinguished Toastmaster - Since 2014

Education:

Bachelor of Science, Clarkson University, 1986.

Master of Science, Syracuse University, 1991.

PRIOR Roles:
IBM Z10 Midrange Lead (2008-2010)
- Leader for the IBM Z10 Business Class Mainframe.

IBM Z10 Pervasive Lead (2006-2010)
- Lead microarchitect for the pervasive logic for the processors, cache, and memory.
- Provided the hardware infrastructure for processor chips (CP, SC, Nova) for clocks, scan, synchronous communication, error reporting, recovery, and host code/millicode support.

IBM Nest RAS Lead (1997 - Present)
- Responsible for ECC codes and RAS innovations around the Processor Cache, Interfaces, and Memory for G6, z900, z800, z990, z890, z9-EC, and z9-BC programs through 2010.
- Innovations around Soft and Hard error resiliancy for IBM Mainframes.
- Continue to be a significant contributor to IBM Z Mainframe Processor Nest/Cache/Memory RAS.

IBM Mainframe Timing Lead (1990-1997)
- Timing and characterization lead for Bipolar 3090 H2/H5 and CMOS G4 & G5 programs.
- Patent leader in cycle time reduction and timing innovation.
- Nest technology bring-up lead for IBM Mainframe G6, z900, z800, z990, and z890.

IBM Mainframe Logic Designer (1986-2011)
- Responsible for delivering Processor Cache/Nest/Memory designs.
- Responsible for VHDL delivery for all major ECC/RAS functions.