Haifeng Qian  Haifeng Qian photo       

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Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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DEGREES

  • Ph.D., University of Minnesota, 2006
  • B.E., Tsinghua University, 2000


RECOGNITIONS

  • Best Paper Award, ACM/IEEE Design Automation Conference, 2003
  • IBM PhD Fellowship, 2005
  • ACM Outstanding Ph.D. Dissertation Award in Electronic Design Automation, 2007
  • IBM Corporate Award, 2013, for Global Clocking Methodology: A Design Environment for Industry-leading High Frequency Global Clocks


SERVICES

  • Associate Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012-2017


PUBLICATIONS (Citations)


PATENTS

  • Simultaneous Power and Timing Optimization in Integrated Circuits by Performing Discrete Actions on Circuit Components, Emrah Acar, Haifeng Qian, U.S. Patent 7689942, 2010.
  • Regular Local Clock Buffer Placement and Latch Clustering by Iterative Optimization, Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock, U.S. Patent 8104014, 2012.
  • Converged Large Block and Structured Synthesis for High Performance Microprocessor Designs, Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan, Ruchir Puri, Haifeng Qian, Haoxing Ren, Chin Ngai Sze, Louise H. Trevillyan, Hua Xiang, Matthew M. Ziegler, U.S. Patent 8271920, 2012.
  • Designing a Robust Power Efficient Clock Distribution Network, Charles J. Alpert, Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle, Chin Ngai Sze, Ying Zhou, U.S. Patent 8677305, 2014.
  • Direct Current Circuit Analysis Based Clock Network Design, Charles J. Alpert, Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle, Chin Ngai Sze, Ying Zhou, U.S. Patent 8775996, 2014.
  • Malicious Activity Detection of a Functional Unit, Chen-Yong Cher, Eren Kursun, Haifeng Qian, U.S. Patent 9088597, 2015.
  • Malicious Activity Detection of a Processing Thread, Chen-Yong Cher, Eren Kursun, Haifeng Qian, U.S. Patent 9218488, 2015.
  • Cross-hierarchy Interconnect Adjustment for Power Recovery, Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha, U.S. Patent 9552451, 2017.
  • Matrix Ordering for Cache Efficiency in Performing Large Sparse Matrix Operations, Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares, U.S. Patent 9606934, 2017.
  • Control Path Power Adjustment for Chip Design, Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha, U.S. Patent 9703910, 2017.


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