John David (John David) Wellman           

I received my Computer Science and Engineering Ph.D. degree in 1996 from the University of Michigan, Ann Arbor, where my thesis work focused on methods for the performance analysis of processor cores, especially dynamic superscalar out-of-order cores. During that period I had spent two summer interships with IBM Research personnel, and had been supported by an IBM Fellowship.

In 1996 I joined IBM Research as a Research Staff Member, then working within the Design Automation department in the area of processor performance modeling as a sub-field of design automation. In this context, I developed a number of tools and infrastructural components which have continued to be used within IBM over the course of the following 15 years. Most notably, I have continued support for Aria (part of the MET toolset) fairly continuously, and several of its library components are still in use today.

I then moved to I moved to the Systems Technology and Microarchitecture department to form part of the IBM Research team that helped to define, for a collaboration between Sony, IBM and Toshiba (targeted to the Playstation-3 console hardware) what was to eventually be marketed as the STI Cell processor. I worked within the formative system and core architectural teams, and with the partners' technical staff to develop the high-level design for that platform. This work was followed by a period where I worked with teams of other researchers to investigate and identify potential commercial uses of STI Cell processor technology; that work ultimately resulted in a series of Cell blade products.

Once the STI Cell project had moved securely into the implementation and development phase, I moved to the PERCS project, which was the government supported competition among the leading high-performance computing system manufacturers, to provide a very powerful supercomputing platform in the 2012 time frame. In the PERCS project I worked within the Research team which worked to define the prospective PERCS core design (and core-side memory hierarchy). I was responsible not only for microarchitectural work, but also the primary designer and lead of the performance evaluation environment, and the local workload analysis team.

With the culmination of the PERCS Phase-2 competition (after which IBM was awarded a contract to produce such a machine) and the PERCS project moved into the implementation and development domain, I shifted focus to the early-stage performance analysis of IBM Mainframe core designs. I continue to work in this domain, providing methods, tools and support for performance analysis in the earlier design stages, when there is a large design space and the project leads are open to considering more drastic design changes. In this role I have contributed to many of the recent IBM Mainframe systems, and continue to do so for future systems.

In the last few years, I have become involved in the IBM Quantum Computing efforts, working to develop and scale up the IBM Q systems offerings by applying my classical computer system design and development skills to the control portion of the Quantum Computer Systems designs.  This is a fascinating application of computer design work in a new area with new stresses, approaches, and requirements.

My research interests have included and continue to include:

• processor and system architecture, design and performance analysis,
• workload characterization and analysis
• design validation (of both hardware and software)
• programming and programming languages; particularly those that can help to bridge between hardware and software
• parallel execution, both multi-core and multi-thread, and supercomputing
• design tools, design automation
• code optimization and performance, particularly in re: simulation performance
• quantum computing (hardware, algorithms, etc.)
• and many other things...

Some of the projects to which I have contributed:

• The MET Toolset (and particularly Aria)
• The STI Cell Processor
• The Cell Blade
• PERCS
• IBM z  Mainframe Systems (z10 core, z196, zEC-12, Z-13, Z-14, and future cores)
• IBM Q Quantum Computing Systems