Jie Yang  Jie Yang photo         

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Device Design and Integration
Albany, Malta
  +1dash203dash843dash4211

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Professional Associations:  American Physical Society (APS)  |  IEEE Electron Devices Society (EDS)  |  IEEE Member  |  Sigma Xi

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Dr. Yang pursued his PhD from Yale University, New Haven, graduated in 2015. In 2011, Dr. Yang worked at IBM Semiconductor Research and Development Center (SRDC) as an intern. Dr. Yang obtained his B.S from Peking University, EECS Department, in 2009. 

During his PhD, Dr. Yang studied the interface physics for Gallium Nitride based power electronics. As an intern at IBM SRDC, Dr. Yang worked on the software development for the data extraction infrastructure and studied the Local Layout Effects on the 22nm hardware. At IBM as a full-time researcher he worked on the next-gen integrated circuit technology: design and fabrication of the nanoscale switches, called FinFET (Fin Field Effect Transistor) made from Silicon Germanium. In this project, he served as Junction Intergraion Module lead and enabled eSiGe process for SiGe FinFET to achieve comparable performance and solving the strain layout dependency issues. From 2016-2018, Dr.Yang leads the device performance step up efforts from IBM side in Globalfoundries 7nm silicon bulk FinFET as a technical assignee, introduced the new trench implant process, combining with nano-second laser annealing, and ramped the process up from early research paper (IEDM, IEEE-EDL) to the full-flown process in 14LPP product elements  and 7LP baseline, with significant performance boosts, and solid SRAM and Logic yield with foundry design IPs.  

Dr. Yang published numerous journal papers in the Applied Physics Letter, IEEE Electronic Device Letter, Transaction on Electronic Devices, Japanese Journal of Applied Physics, conference papers in IEDM, VLSI, DRC etc, serves as a reviewer for aforementioned journals as well as  IEEE Transaction on Semiconductor Manufacturing, Journal of the Electron Devices Society, Solid State Electronics and etc.