Dr. Kubilay Atasu obtained in his BSc. and PhD. degrees in Computer Engineering from Bogazici University, Istanbul in 2000 and in 2008, respectively. Before joining IBM Research - Zurich in 2008, he held research positions at Swiss Federal Institute of Technology Lausanne (EPFL) and at Imperial College London, where he worked on design automation of application-specific processors. At IBM Research, he initially contributed to the design and development of hardware accelerators on IBM's PowerEN (Edge-of-Network) processor. Later, he led design and development of reconfigurable accelerators for high-speed text analytics. Currently, he is developing scalable algorithms and architectures for large-scale graph processing and machine learning.
Dr. Atasu was the recipient of a best paper award at the Design Automation Conference (DAC) in 2003, and at the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) in 2008. He was a program co-chair of the ASAP 2013 Conference, and a general co-chair of the ASAP 2014 Conference. Dr. Atasu has served in the program committees of ASAP, FPL, FPT DATE, ICPP, ISPDC, and CF conferences, and is a member of the Editorial Board of Springer's Journal of Signal Processing Systems (JSPS). In Spring 2016, he taught the "Parallel Computer Architecture" course at the University of Tuebingen to final-year BSc. and first-year MSc. students. Since May 2018, he is a Senior Member of IEEE.