Dr. Kubilay Atasu obtained in his BSc. and PhD. degrees in Computer Engineering from Bogazici University, Istanbul in 2000 and in 2008, respectively. Before joining IBM Research - Zurich in 2008, he held research positions at Swiss Federal Institute of Technology Lausanne (EPFL) and at Imperial College London, where he worked on design automation of application-specific processors. In summer 2006, he was a visiting researcher at Stanford University. At IBM Research, he initially contributed to the design and development of regular expression accelerators on IBM's PowerEN (Edge-of-Network) processor. Later, he led the design and development of reconfigurable hardware accelerators for high-speed text analytics. Currently, he is developing scalable algorithms and hardware architectures for high-performance graph processing and machine learning.
Dr. Atasu was the recipient of a best paper award at the Design Automation Conference (DAC) in 2003, and at the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) in 2008. He was a program co-chair of the ASAP 2013 Conference, and a general co-chair of the ASAP 2014 Conference. Dr. Atasu is serving in the program committees of FCCM, CF, ASAP, and FPL conferences. In the past, he also served in the program committees of FPT, DATE, ICPP, ISPDC, and SDS conferences. He is a member of the Editorial Board of Springer's Journal of Signal Processing Systems (JSPS). In Spring 2016, he taught the "Parallel Computer Architecture" course at the University of Tuebingen to final-year BSc. and first-year MSc. students. His research activities are partly funded by SNSF. He is a Senior Member of IEEE.