Kubilay Atasu  Kubilay Atasu photo         

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Research Staff Member
Zurich Research Laboratory, Zurich, Switzerland
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Professional Associations:  IEEE, Senior Member

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Dr. Atasu  joined IBM Research – Zürich in 2008 after obtaining his BSc. and PhD. degrees in Computer Engineering from Boğaziçi University, Istanbul in 2000 and in 2008, respectively.  He also holds a MEng. degree in Embedded System Design from University of Lugano. Before joining IBM Research – Zurich, he held research positions at Swiss Federal Institute of Technology Lausanne (EPFL) and at Imperial College London, where he worked on design automation of application-specific processors. In summer 2006, he was a visiting researcher at Stanford University.  In Spring 2016, he was an adjunct lecturer at the University of Tübingen. Since October 2020, he is a visiting faculty member at Sabanci University, Istanbul, where he is lecturing on parallel computer architectures and graph mining.

At IBM Research, Dr. Atasu initially contributed to the design and development of IBM’s PowerEN (Edge-of-Network) processor. Later, he led the design and development of FPGA-based hardware accelerators for high-speed text analytics. Currently, he is developing scalable algorithms and hardware architectures for high-performance graph processing and machine learning. His research activities are partly funded by SNSF.

Dr. Atasu was the recipient of a best paper award at the Design Automation Conference (DAC) in 2003, and at the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) in 2008. He was a best-paper award nominee at the International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He served as a program co-chair of the ASAP 2013 Conference and as a general chair of the ASAP 2014 Conference, which took place at IBM’s Zurich Research Laboratory. Dr. Atasu is currently serving in the program committees of DAC, FCCM, CF, ASAP, FPL and FPT conferences. In the past, he also served in the program committees of DATE, ICPP, ISPDC, and SDS conferences. He is a Senior Member of IEEE and a member of the Editorial Board of Springer’s Journal of Signal Processing Systems (JSPS).