High Speed I/O Design - overview
An important research topic is the design of compact low-power I/O transceivers for both chip-to-chip and backplane communication applications. Industry standards are being developed to define compliant channel and I/O electrical characteristics for operation at data rates from 6+ to 11+ Gb/s for both short-range ( -in, on-board) interchip links such as CPU memory applications and long-range backplane ( -in , intercard) or coax ( 10 m+) links that arise in systems such as scalable multiple- processor servers and high-speed routers/switches. The focus of our work is on low-voltage, low-power circuit design in the most advanced CMOS and CMOS SOI technologies.The goal is to integrate a multitude of high-speed links on a single digital chip, thereby achieving multi-Terabits/s aggregate bandwidth at low power consumption and small chip area.
To enable reliable operation on dispersive channels that produce significant intersymbol interference (ISI) at a given symbol (or baud) rate as shown below, the I/O core architecture can employ some form of line equalization. A common approach to equalization for data rates up to 3-4 Gb/s is "feed-forward" equalization, or FFE, at the transmitter, which predistorts the signal such that it is recovered at the receiver with a desired shape suitable for reliable data detection. Another form of equalizer is the "decision-feedback" equalizer, or DFE, which operates by subtracting the ISI arising from previously detected data symbols from the symbol currently being received. The DFE operates as a nonlinear equalizer and can recover data that have been severely degraded by the distortion/noise arising from channel loss, reflections, and high-frequency crosstalk. All of these impairments can distort the signal beyond the capability of an FFE alone to equalize for reliable operation at 6-Gb/s+ data rates over backplane channels. Below a two-port I/O core microphotograph is shown.
The introduction of dense, fine-pitch silicon packaging technologies, in principle capable of supporting tens of thousands of high data rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent. An example of such a dense packaging technology is silicon carrier, in which chips to be packaged are mounted on a silicon substrate and inter-chip signaling is supported with dense back end of line (BEOL) copper wires. Figure depicts two chips mounted on a silicon carrier, connected to each other using dense BEOL wires. Signals are transmitted and received by the I/O circuits on the two chips; the two chips communicate to the outside world via through-silicon vias. To capitalize on the potential advantages of the silicon carrier packaging technology, however, compact and low-power I/O circuitry suited to the silicon carrier's channel characteristics must be developed. The challenge of compact I/O in silicon carrier links is achieving the performance of a high tap-count DFE without paying an unacceptable area and power penalty. To meet this challenge, a modified DFE with IIR filter feedback (DFE-IIR), which takes advantage of silicon carrier channel characteristics to enable efficient equalization of carrier channel loss has been designed.