Computer Architecture     


Computer Architecture - overview

At its core, IBM is a computer company; and IBM researchers have made seminal contributions to the computer architecture field. Here are some of our exciting research activities in the computer architecture area.

IBM Computer Architecture Projects

Recent Publications

  • "A Model for Fusion and Code Motion in an Automatic Parallelizing Compiler," Uday Bondhugula, Oktay Gunluk, Sanjeeb Dash, Lakshminarayanan Renganarayana, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
  • "DMATiler: Revisiting Loop Tiling for Direct Memory Access (Extended Abstract)," HaiBo Lin, Tao Liu, Huoding Li, Tong Chen, Lakshminarayanan Renganarayana, Kevin O\'Brien, Ling Shao, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
  • "Trends and Techniques for Energy Efficient Architectures," Victor Jimenez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), 2010.
  • "Power-efficient, reliable microprocessor architectures: modeling and design methods," Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta S. Gupta, Hendrik Hamann, Hans Jacobson, Prabhakar N. Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor Zyuban, Proceedings of the 20th symposium on Great lakes symposium on VLSI (GLVLSI), 2010.
  • "A Wire-Speed Power (TM) Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads," C. Johnson, D. H. Allen, J. Brown, S. Vanderwiel, R. Hoover, H. Achilles, C-Y. Cher, G. A. May, H. Franke, J. Xenedis, C. Basso, 2010 IEEE International Solid-State Circuits Conference (ISSCC).

See our publication page for more.

Recently issued patents

  • Method and System for Multiprocessor Emulation on a Multiprocessor Host System, 11/30/2010, US patent 7844446, John O'Brien, Kathryn O'Brien, Erik Altman, Daniel Prener, Peter H Oden, Ravi Nair, Sumedh Sathaye
  • Method and apparatus for application-specific dynamic cache placement, 11/16/2010, US Patent 7836256, Krishnan Kailas, Rajiv Ravindran, Zehra Sura.
  • Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores, 10/19/10, US patent 7818696, Pradip Bose, Malcolm Ware, Srinivasan Ramani, Ken Vu.
  • Processor bus for performance monitoring with digests, 10/19/10, US Patent 7818624, Ravi Nair, Hillery Hunter.
  • DRAM cache with on-demand reload, 9/28/10, US patent 7805658, Wing Kin Luk, Ravi Nair.
  • Method, system, and computer program product for path-corrrelated indirect addres predictions, 9/14/10, US patent 7797521, Richard Eickemeyer, Robert Philhower, Ravi Nair, Michael Gschwind
  • Method and apparatus for preventing soft error accumulation in register arrays, 8/10/10, US patent 7774654, Balaram Sinharoy, Pradip Bose, Victor Zyuban, Jude Rivers.
  • Alignment of cache fetch return data relative to a thread, 5/25/10, US patent 7725659, Hans Jacobson, Robert Philhower, Michael Gschwind

A list of all US patents issued since 2010 in the related areas can be found here.

Recent Faculty Awards and PhD Fellowships

Here are some recent IBM university relationship awards given to the faculty and students in the Computer Architecture area. Some of our past university collaborators can be found here.

Faculty Awards

PhD Fellowships

What's new?

Upcoming Seminars

  • November 4, 2010
    Architecture, Design, and Implementation of a 3D-IC Many-core Processor, Prof. Hsien-Hsin S. Lee, Georgia Institute of Technology.
  • November 5, 2010
    Understanding the memory systems of a modern NUMA Processor, Prof. Thomas Gross, ETH Zurich.

A complete list of recent seminars can be found here.