eLite DSP Project - overview
Embedded Low-Power Digital Signal Processor Project
The world is going wireless, and Digital Signal Processors (DSPs) are accelerating this trend. DSPs have become an ubiquitous enabler for the integration of audio, video, and communications. Often, DSPs and general-purpose processors (microcontrollers) are found in the same system. The new generations of DSPs are adding general-purpose control features to their capabilities, while microcontrollers are adding DSP features as well, thereby blurring the once well-established boundaries between such processors.
A large number of standards exist or have been proposed for the wireless and wired communication domains. Such a diversity of standards, and their continued evolution, demands a programmable platform that can be easily adapted to the specific requirements. Another important aspect is the increase in performance requirements. In the GSM and IS-54 standard, data rates are 8 to 14 Kbps. In contrast, in the third generation standards (3G) the data rates are 64 Kbps (mobile), 384 Kbps (pedestrian), and 2 Mbps (close stationary). Wireless LAN networks are already operating at 11 Mbps, while some proprietary implementations have increased this throughput fivefold. Wired communications are experiencing a similar trend; previous generation v.90 modems were limited to 56 Kbps, whereas new ADSL standards specify up to 8 Mbps and future VDSL standards may specify 52 Mbps. All these high communication rates are driving much higher DSP processing requirements.
Other signal processing and media processing domains are experiencing similar growths in computing requirements. Voice recognition algorithms with higher accuracy rely on a much higher computational load. Video decoding and encoding standards impose computational loads directly proportional to the resolution of the image, which is continuously increasing.
In addition to the high computing needs, complexity is driving the need to program the applications in high-level languages. In the past, when only small kernels were required to execute on a DSP, it was acceptable to program them in Assembly language. Given the increased complexity of contemporary applications, characterized by a large number of lines of code written in a high-level programming language, the new generations of DSP applications are expected to be programmed mostly in high-level languages.
DSPs have distinct requirements when compared with general purpose CPUs. The predominant algorithmic difference is that inner loops are easily described as moderate length vectors. A typical DSP kernel is an FIR filter which can be described mathematically as y(k)=S c(n) x(k-n). From this kernel, it is apparent that multiple concurrent memory accesses are required to sustain performance. Generally, one instruction and two data values are required each cycle; the operations required include two address pointer updates, a multiply operation and the accumulate operation. Often, the result should additionally be rounded or saturated. A key point is that the native data type is fixed-point (e.g., fractional arithmetic). This is in distinct contrast to general purpose processors (and most high-level languages) which operate on integer data types.
In addition to algorithmic differences, DSPs are frequently deployed in embedded environments wherein real-time constraints are prevalent. Real-time behavior has a dominant influence in the design of DSPs. Whereas general-purpose applications can usually manage under responses of varying latency, DSP applications are required to guarantee the latencies within the system. Such execution predictability precludes or restricts the use of general-purpose performance enhancing techniques, such as speculation, branch prediction, data caches, etc. Instead, DSPs have developed a unique set of techniques that are optimized for their intended market.
eLite DSP Contributions
The Embedded Low-Power Digital Signal Processor project (eLite DSP), an ongoing effort within IBM Research and Development, is advancing the state of the art in power-efficient programmable DSP architectures as well as methodologies for such type of designs. This effort grows from the understanding that the important matter is an architecture that provides a balanced optimization of programmability in high-level language, power consumption, performance, development cost (hardware and software), and production cost (chip and system). In order to achieve these usually conflicting optimization goals, the design of the eLite DSP architecture and its implementations covers aspects ranging from algorithms, applications, and high-level language compiler, down to circuit-level technology. The resulting architecture is a multiple-issue statically scheduled processor, with a heterogeneous set of register files spread throughout specialized units. Parallelism is achieved by executing multiple instructions operating on different registers (VLIW), in conjunction with single instructions operating on different registers (single instruction multiple disjoint data, SIMdD), as well as single instructions operating on packed data (single instruction multiple packed data SIMpD). A novel indirect register addressing mechanism enables the dynamic composition of vectors with four elements selected from a large multiported register file.The eLite DSP has as objective the development of a low power embedded DSP capable of sustaining 1 billion multiply-accumulate operations per second (1 GMACs) while consuming only 20 mW of power when implemented in foundry CMOS technology and operating at low voltage. Operational frequency, and consequently computational throughput, increases to 2 GMACs at higher voltage while consuming only 200 mW. Due to its low power consumption, the eLite DSP is ideal for mobile handsets. On the other hand, the frequency scaling possible with voltage scaling enables base-station applications that can also significantly benefit from this processor.
The unique research contributions arising from the eLite DSP include more than just an architecture and an implementation. Other salient aspects are a power-performance methodology at the architecture level; new circuit techniques for ultra-low power implementations; important compiler optimizations for DSP operations; and system level design experience.
Throughout this site, we provide a description of the eLite DSP architecture, the associated optimizing compiler, the integrated development environment available, details of the ultra-low power implementation, and the applications which this architecture is targeting. The description includes our research publications. list of patent applications that have been filed, and presentations on the subject.