Storage Class Memory at Almaden     

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Noel Arellano photoGeoffrey W. Burr photoSteve Guendert photoERIC A. JOSEPH photo Hiroyuki (Hiro) Miyazoe photo Pritish Narayanan photoCharles T. Rettner photo Kevin P Roche photoLeslie E. Thompson photo

Storage Class Memory at Almaden - overview


Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sub-lithographic patterning techniques, multiple bits per cell, and multiple layers of devices.

Overview presentations

  1. " Storage Class Memory Overview "
  2. "SCMandMIEC_overview_12Feb2013 "

Major Publications

  1. "Large-scale neural networks implemented with nonvolatile memory as the synaptic weight element: comparative performance analysis (accuracy, speed, and power)," G. W. Burr, P.Narayanan, R.M.Shelby, S. Sidler, I.Boybat, C.di Nolfo, and Y.Leblebici, 2015 IEEE International Electron Devices Meeting (IEDM 2015), invited talk, 4.4, December 2015.

     

  2. "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element," G. W. Burr, R. M. Shelby, C. di Nolfo, J. W. Jang, R. S. Shenoy, P. Narayanan, K. Virwani, E. U. Giacometti, B. Kurdi, and H. Hwang, 2014 IEEE International Electron Devices Meeting (IEDM 2014), 29.5, December 2014.

     

  3. "Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays," P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B. Kurdi, 2014 IEEE International Electron Devices Meeting (IEDM 2014), 29.7, December 2014.

     

  4. " Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed-Ionic-Electronic-Conduction (MIEC)-based access devices," P. Narayanan, G. W. Burr, R. S. Shenoy, S. Stephens, K. Virwani, A. Padilla, B. Kurdi, and K. Gopalakrishnan, Device Research Conference, V.-A5, June 2014.

     

  5. "The origin of massive nonlinearity in mixed-Ionic-Electronic-Conduction (MIEC)-based access devices, as revealed by numerical device simulation," A. Padilla, G. W. Burr, R. S. Shenoy, K. V. Raman, D. Bethune, R. M. Shelby, C. T. Rettner, J. Mohammad, K. Virwani, P. Narayanan, A. K. Deb, R. K. Pandey, M. Bajaj, K. V. R. M. Murali, B. N. Kurdi, and K. Gopalakrishnan, Device Research Conference, poster III-53, June 2014.

     

  6. "Recovery dynamics and fast (sub-50ns) read operation with Access Devices for 3D Crosspoint Memory based on Mixed-Ionic-Electronic-Conduction (MIEC)," G. W. Burr, K. Virwani, R. S. Shenoy, G. Fraczak, C. T. Rettner, A. Padilla, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan, 2013 Symposium on VLSI Technology, T6.4, June 2013.

     

  7. "Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials," K. Virwani, G. W. Burr, R. S. Shenoy, C. T. Rettner, A. Padilla, T. Topuria, P. M. Rice, G. Ho, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, M. BrightSky, E. A. Joseph, A. J. Kellock, N. Arellano, B. N. Kurdi and K. Gopalakrishnan, 2012 IEEE International Electron Devices Meeting (IEDM 2012), December 2012.

     

  8. "Large-scale (512kbit) integration of Multilayer-ready Access-Devices based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% yield," G. W. Burr, K. Virwani, R. S. Shenoy, A. Padilla, M. BrightSky, E. A. Joseph, M. Lofaro, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, C. T. Rettner, B. Jackson, D. S. Bethune, R. M. Shelby, T. Topuria, N. Arellano, P. M. Rice, B. N. Kurdi, and K. Gopalakrishnan, 2012 Symposium on VLSI Technology, T5-4, June 2012.

     

  9. "Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint-Memory based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials," R. S. Shenoy, K. Gopalakrishnan, B. Jackson, K. Virwani, G. W. Burr, C. T. Rettner, A. Padilla, D. S. Bethune, R. M. Shelby, A. J. Kellock, M. Breitwisch, E. A. Joseph, R. Dasaka, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, 2011 Symposium on VLSI Technology, T5B-1, June 2011.
  10. "Highly-Scalable Novel Access Device based on Mixed Ionic Electronic Conduction (MIEC) Materials for High Density Phase Change Memory (PCM) Arrays," K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, D. S. Bethune, R. M. Shelby, G. W. Burr, A. J. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, 2010 Symposium on VLSI Technology, 19.4, June 2010.

 

 

Review Articles

  1. "Access devices for 3-D crosspoint memory," G. W. Burr, R. S. Shenoy, P. Narayanan, K. Virwani, A. Padilla B. Kurdi, and H. Hwang, Journal of Vacuum Science & Technology B, 32(4), 040802 (2014).

     

  2. "Phase change memory technology," G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran, S. Raoux, and R. Shenoy, Journal of Vacuum Science & Technology B, 28(2), 223-262 (2010).

     

  3. "Storage-class memory: The next storage system technology," R. Freitas and W. W. Wilcke, IBM Journal of Research and Development, 52(4/5), 439-448 (2008).

     

  4. "Overview of candidate device technologies for Storage-Class Memory," G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, IBM Journal of Research and Development, 52(4/5), 449-464 (2008).

     

  5. "Phase change Random Access Memory - A Scalable Technology," S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam, IBM Journal of Research and Development, 52(4/5), 465-480 (2008).