High-Density Silicon Carrier Transmission Line Design for Chip-to-Chip Interconnects - overview

Two differential stripline configurations with pitches of 8μm and 22μm are designed for ultra dense interconnect on silicon carrier. The transmission lines are implemented using four wiring levels to support chip-to-chip communication at 11.5Gb/s data rate over 2cm without equalization. Loss characteristics are extracted from test coupons with good model-to-hardware correlation. Impedance and temperature dependent loss performance are analyzed with simulation. Crosstalk performance between two pairs with and without ground shielding, as well as between two twisted pairs, are also evaluated with hardware measurement. (EPEPS'11)

Illustration of silicon carrier link concept Cross-sections of silicon carrier metals layers, and M2 and M3 striplines