3D Semiconductor & Packaging Technology for Systems     


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3D Semiconductor & Packaging Technology for Systems - overview

Three dimensional (3D) semiconductor and packaging technology using through-silicon-vias (TSVs) are used to stack thinned semiconductor chips and to integrate heterogeneous semiconductor technologies into micro-electronic modules.


These microelectronic modules permit miniaturization which can be applied to portable microelectronics systems including: smart-phones, sensors and bio-medical solutions. The modules can also be applied to large computing systems such as servers and super-computers as well as many other applications.

Product applications can benefit from 3D technology to improve performance, increase bandwidth, improve power efficiency, and reduce costs.

The 3D technology is developed at IBM’s Thomas J. Watson Research Center and other IBM Research laboratories around the world.

The IBM research teams drive 3D technology advancements including: materials, structures, processes and equipment to develop semiconductor wafer fabrication processes compatible with TSV’s, wafer thinning and backside processing.

The research team also drives design and 3D integration technology advancements such as bond and assembly, test, module integration, power delivery and thermal / cooling solutions to support multiple generations of the technology for product applications.

The team designs and builds test hardware to develop processes and design rules that can be used with each next generation of 3D technology and corresponding device node for future manufacturing applications that support IBM and our worldwide customers.

The research team has been developing 3D technology for more than a decade and first products began shipping from IBM manufacturing in 2008.

Research Data and Demonstration Examples:

  1. Design & Modeling as for electrical power distribution assessments in 3D chip stacks:
  2. distribution in 3D chip stacks
  3. 45nm device with thin chip stack using TSV & Micro-bump solder
  4. 45nm device with thin chip stack
  5. Multi-chip Module with multiple thin chip-stacks and fine pitch interconnections on a silicon package.
  6. Multi-chip Module